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| ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE PM7385 FREEDM-84A672 FRAME ENGINE AND DATALINK MANAGER 84A672 PROGRAMMER'S GUIDE PROPRIETARY AND CONFIDENTIAL ADVANCE ISSUE 1: JUNE 1999 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE CONTENTS 1 INTRODUCTION ......................................................................................1 1.1 1.2 1.3 1.4 SCOPE ..........................................................................................1 TARGET AUDIENCE .....................................................................1 NUMBERING CONVENTIONS......................................................1 REGISTER DESCRIPTION ...........................................................1 1.4.1 NORMAL MODE REGISTERS............................................2 2 3 REFERENCES .........................................................................................3 FREEDM-84A672 OVERVIEW.................................................................4 3.1 3.2 4 FREEDM-84A672 SUMMARY .......................................................4 ANY-PHY PACKET INTERFACE ...................................................7 INTERRUPT ARCHITECTURE ................................................................9 4.1 4.2 NON-SBI INTERRUPTS ................................................................9 SBI INTERRUPTS .........................................................................9 5 CONFIGURING THE SBI INTERFACE .................................................. 11 5.1 5.2 CONFIGURING THE SBI DROP BUS ......................................... 11 CONFIGURING THE SBI ADD BUS ............................................12 6 CONFIGURING THE SBI EXTRACTER AND INSERTER .....................15 6.1 CONFIGURING THE SBI EXTRACTER ......................................15 6.1.1 SBI EXTRACT CONTROL ................................................15 6.1.2 SBI EXTRACT TRIBUTARY CONFIGURATION ...............16 6.2 CONFIGURING THE SBI INSERTER..........................................18 6.2.1 SBI INSERT CONTROL ....................................................18 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE i ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 6.2.2 SBI INSERT TRIBUTARY CONFIGURATION ...................19 7 CONFIGURING THE SERIAL LINKS .....................................................21 7.1 7.2 8 SBI SPE/TRIBUTARY LINKS.......................................................25 CLOCK/DATA LINKS ...................................................................27 CONFIGURING THE ANY-PHY PACKET INTERFACE..........................30 8.1 8.2 CONFIGURING THE RECEIVE ANY-PHY PACKET INTERFACE (RAPI672) ....................................................................................30 CONFIGURING THE TRANSMIT ANY-PHY PACKET INTERFACE (TAPI672).....................................................................................32 9 HDLC AND CHANNEL FIFO CONFIGURATION....................................35 9.1 9.2 9.3 CONFIGURING THE RHDL672...................................................35 CONFIGURING THE THDL672 ...................................................36 PROGRAMMING A CHANNEL FIFO ...........................................37 9.3.1 RECEIVE CHANNEL FIFO ...............................................38 9.3.2 TRANSMIT CHANNEL FIFO .............................................39 9.4 9.5 RHDL672 CHANNEL CONFIGURATION.....................................40 THDL672 CHANNEL CONFIGURATION .....................................43 10 FREEDM-84A672 OPERATIONAL PROCEDURES...............................49 10.1 10.2 10.3 10.4 10.5 10.6 DEVICE IDENTIFICATION, LOCATION AND SYSTEM RESOURCE ASSIGNMENT ........................................................49 RESET .........................................................................................49 INITIALIZATION...........................................................................50 ACTIVATION PROCEDURE ........................................................51 DEACTIVATION PROCEDURE ...................................................51 PROVISIONING A CHANNEL......................................................52 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE ii ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 10.6.1 RECEIVE CHANNEL PROVISIONING .............................52 10.6.2 TRANSMIT CHANNEL PROVISIONING...........................54 10.7 UNPROVISIONING A CHANNEL ................................................57 10.7.1 RECEIVE CHANNEL UNPROVISIONING ........................57 10.7.2 TRANSMIT CHANNEL UNPROVISIONING......................59 10.8 10.9 RECEIVE SEQUENCE ................................................................62 TRANSMIT SEQUENCE..............................................................62 10.10 PERFORMANCE COUNTERS ....................................................62 10.11 LINE LOOPBACK ........................................................................65 10.12 DIAGNOSTIC LOOPBACK ..........................................................66 APPENDIX A - REGISTER LEVEL CHANGES ................................................67 APPENDIX B - NEW NORMAL MODE REGISTERS .......................................76 APPENDIX C - NON-APPLICABLE NORMAL MODE REGISTERS ................78 APPENDIX D - MOVED NORMAL MODE REGISTERS ..................................80 APPENDIX E - NORMAL MODE REGISTER BIT CHANGES .........................81 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE iii ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE LIST OF FIGURES FIGURE 1 - FREEDM-84A672 BLOCK DIAGRAM ............................................6 FIGURE 2 - RECEIVE LINK TIMING................................................................28 FIGURE 3 - TRANSMIT LINK TIMING .............................................................28 FIGURE 4 - SPECIFYING A CHANNEL FIFO ..................................................38 FIGURE 5 - EVENT SEQUENCE FOR POLLING OF COUNTERS.................63 FIGURE 6 - LINE LOOPBACK .........................................................................65 FIGURE 7 - DIAGNOSTIC LOOPBACK...........................................................66 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE iv ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 1 1.1 INTRODUCTION Scope The FREEDM-84A672 Programmer's Guide describes the configurable features and operation of a FREEDM-84A672 from a programmer's perspective. This document may not cover all applications of the FREEDM-84A672. Please contact a PMC-Sierra Applications Engineer for specific uses not covered in this document. This document is a supplement to the FREEDM-84A672 Longform Datasheet[1]. Both documents should be studied together to interface the FREEDM-84A672 to an embedded processor. In case of a discrepancy between the Programmer's Guide and the Longform Datasheet, the Longform Datasheet shall always be considered correct. 1.2 Target Audience The FREEDM-84A672 Programmer's Guide describes the configuration and initialisation necessary for programming the FREEDM-84A672 from a programmer's perspective. This document has been prepared for readers with prior knowledge of the HDLC protocol. 1.3 Numbering Conventions The following numbering conventions are used throughout this document: binary decimal hexadecimal 011 1010B, 011 129, 6, 12 0x1FE2, 09FH 1.4 Register Description Unless specified, FREEDM-84A672 registers are described using the convention REGISTER_NAME (address in FREEDM-84A672). There is only one register space that can be addressed on a FREEDM-84A672, and it consists of the normal mode microprocessor accessible registers. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 1 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 1.4.1 Normal Mode Registers Normal mode registers are used to configure, monitor and control the operation of the FREEDM-84A672. Registers must be accessed as 16-bit values with a dword aligned address. For all register descriptions, the hexademical register number indicates the address in the FREEDM-84A672 when accesses are made using the external microprocessor. A register value is accessed through an external microprocessor and has the following characteristics: * Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits should be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software during a register read access. Except where noted, all configuration bits that can be written into can also be read back. This allows the processor controlling the FREEDM-84A672 to determine the programming state of the block. Writable normal mode registers are cleared to logic zero upon reset unless otherwise noted. Writing into read-only normal mode register bit locations does not affect FREEDM-84A672 operation unless otherwise noted. Certain register bits are reserved. These bits are associated with megacell functions that are unused in this application. To ensure that the FREEDM84A672 operates as intended, reserved register bits must only be written with their default values. Similarly, writing to reserved registers should be avoided. * * * * PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 2 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 2 REFERENCES 1. PMC-990114, PMC-Sierra, Inc., "Frame Engine and Data Link Manager 84A672" Longform Datasheet, January 1999, Issue 1. 2. PMC-960758, PMC-Sierra, Inc., "Frame Engine and Data Link Manager" Longform Datasheet, May 1998, Issue 5. 3. PMC-980577, PMC-Sierra, Inc., "Saturn Compatible Scaleable Bandwidth Interconnect (SBI) Specification", October 1998, Issue 3. 4. PMC-990263, PMC-Sierra, Inc., "Frame Engine and Data Link Manager 32A672" Longform Datasheet, May 1999, Issue 2. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 3 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 3 3.1 FREEDM-84A672 OVERVIEW FREEDM-84A672 Summary The PM7384 FREEDM-84A672 Frame Engine and Datalink Manager is an advanced data link layer processor that is ideal for applications such as IETF PPP interfaces for routers, Frame Relay switches and multiplexors, ATM switches and multiplexors, Internet/Intranet access equipment, packet-based DSLAM equipment, Packet over SONET, and PPP over SONET. The FREEDM84A672 implements HDLC processing for a maximum of 672 bi-directional channels. The functional blocks of the FREEDM-84A672 are illustrated in Figure 1. The FREEDM-84A672 may be configured to support channelised T1/J1/E1 or unchannelised DS-3 traffic on up to 84 links conveyed via a Scaleable Bandwidth Interconnect (SBI) interface. The SBI interface transports data in three Synchronous Payload Envelopes (SPEs), each of which may be configured independently to carry either 28 T1/J1 links, 21 E1 links or a single DS-3 link. For channelised T1/J1/E1 links, the FREEDM-84A672 allows up to 672 bidirectional HDLC channels to be assigned to individual time-slots within each independently timed T1/J1 or E1 link. These links are processed by the Receive Channel Assigner (RCAS672) and the Transmit Channel Assigner (TCAS672). The channel assignment supports the concatenation of time-slots (N x DS0) up to a maximum of 24 concatenated time-slots for a T1/J1 link and 31 concatenated time-slots for an E1 link. Time-slots assigned to any particular channel need not be contiguous within a T1/J1 or E1 link. Unchannelised DS-3 links are assigned to a single HDLC channel. Additionally, links may be configured independently to operate in an unframed or "clear channel" mode, in which the bit periods which are normally reserved for framing information in fact carry HDLC data. In unframed mode, links operate as unchannelised (i.e. the entire link is assigned to a single HDLC channel) regardless of link rate. The FREEDM-84A672 supports mixing of channelised T1/J1/E1 and unchannelised or unframed links. The total number of channels in each direction is limited to 672. The maximum possible data rate over all links is 134.208 Mbps (which occurs with three DS-3 links running in unframed mode). The FREEDM-84A672 supports three independently timed bidirectional clock/ data links, each carrying a single unchannelised HDLC stream. The links can be PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 4 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE of arbitrary frame format and can operate at up to 52 MHz provided SYSCLK is running at 40 MHz. When activated, each link replaces one of the SPEs PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 5 ADVANCE PMC-990716 APPLICATION NOTE FASTCLK R EFC LK RSTB SPE1_EN SPE3_EN SPE2_EN SYSC LK C1FP C 1FPOUT PM C TEST RCLK[2:0] RD[2:0] SBI PISO SB I Extract SBI PISO SBI PISO Performance Monitor (PMON) Receive Channel Assigner (R CAS672) Receive HDLC Processor / Partia l Packet Buffer (RHDL672) Receive Any-PHY Packet Inte rface (RAPI672) ISSUE 1 DDATA[7:0] DPL DV5 DD P RXCLK RXADDR[2:0] RPA REN B RXDATA[1 5:0] RXP RTY RSX REOP RMOD RERR RVAL SBI SIPO SBI Insert SBI SIPO SBI SIPO Tra nsm it Channel Assigner (TCAS672) Figure 1 - FREEDM-84A672 Block Diagram ADATA[7:0] APL AV5 AD P AJUST_REQ AACTIVE ADETEC T[1:0] Transmit HD LC Processor / Partia l Packet Buffer (THD L672) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE TCLK[2:0] TD[2:0] Microprocessor Inte rface JTAG Port Tra nsm it Any-PHY Packet Inte rface (TAPI6 72) TXCLK TXADD R[12:0] TPA1[2:0] TPA2[2:0 ] TR D Y TXD ATA[15 :0 ] TXPR TY TSX TEO P TMO D TER R 6 PM7385 FREEDM-84A672 IN TB RDB W RB CSB ALE A[11:2] D[15:0] TD O TD I TC K TM S TR STB PROGRAMMER'S GUIDE ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE conveyed on the SBI interface. (The maximum possible data rate when all three clock/data links are activated is 156 Mbps.) Each data stream can be HDLC processed on a channelised basis within the Receive HDLC Processor / Partial Packet Buffer (RHDL672) and Transmit HDLC Processor / Partial Packet Buffer (THDL672). There is a 32 Kbyte buffer in the RHDL672 and another 32 Kbyte buffer in the THDL672 that must be assigned to FREEDM-84A672 channels to serve as channel FIFOs. Each buffer is a group of 2048 blocks with 16 bytes per block, and a minimum of 3 blocks must be assigned to a channel during provisioning. This allows for flexible assignment of a channel FIFO based on the expected data rate for the channel. Alternatively, the RHDL672 and THDL672 can provision a channel as transparent, in which case, the raw data stream is transferred without HDLC processing. The Receive Any-PHY Interface (RAPI672) provides a low latency path for transferring data out of the partial packet buffer in the RHDL672 and onto the Receive Any-PHY Packet Interface (Rx APPI). The RAPI672 contains a FIFO block for latency control as well as to segregate the APPI timing domain from the SYSCLK timing domain. The RAPI672 contains the necessary logic to manage and respond to device polling from an upper layer device. The RAPI672 also provides the upper layer device with status information on a per packet basis. The Transmit Any-PHY Interface (TAPI672) provides a low latency path for transferring data from the Transmit Any-PHY Packet Interface (Tx APPI) into the partial packet buffer in the THDL672. The TAPI672 contains a FIFO block for latency control as well as to segregate the APPI timing domain from the SYSCLK timing domain. The TAPI672 contains the necessary logic to manage and respond to channel polling from an upper layer device. The PMON block provides performance monitor counts for a number of events. These counters can be read via the microprocessor interface and provides a means for the host software to accumulate performance statistics. Links can be individually placed in line loopback. There is also an internal diagnostic loopback configuration for each channel which can be used to diagnose FREEDM-84A672 operation on a per channel basis. 3.2 Any-PHY Packet Interface The FREEDM-84A672 provides a low latency "Any-PHY" Packet Interface (APPI) to allow an external controller direct access into the 32 Kbyte partial packet buffers. Up to seven FREEDM-84A672 devices may share a single APPI. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 7 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE For each of the transmit and receive APPI, the external controller is the master of each FREEDM-84A672 device sharing the APPI from the point of view of device selection. The external controller is also the master for channel selection in the transmit direction. In the receive direction, however, each FREEDM-84A672 device retains control over selection of its respective channels. The transmit and receive APPI is made up of three groups of functional signals - polling, selection and data transfer. The polling signals are used by the external controller to interrogate the status of the transmit and receive 32 Kbyte partial packet buffers. The selection signals are used by the external controller to select a FREEDM84A672 device, or a channel within a FREEDM-84A672 device, for data transfer. The data transfer signals provide a means of transferring data across the APPI between the external controller and a FREEDM-84A672 device. In the receive direction, polling and selection are done at the device level. Polling is not decoupled from selection, as the receive address pins serve as both a device poll address and to select a FREEDM-84A672 device. In response to a positive poll, the external controller may select that FREEDM84A672 device for data transfer. Once selected, the FREEDM-84A672 prepends an in-band channel address to each partial packet transfer across the receive APPI to associate the data with a channel. A FREEDM-84A672 must not be selected after a negative poll response. In the transmit direction, polling is done at the channel level. Polling is completely decoupled from selection. To increase the polling bandwidth, up to two channels may be polled simultaneously. The polling engine in the external controller runs independently of other activity on the transmit APPI. In response to a positive poll, the external controller may commence partial packet data transfer across the transmit APPI for the successfully polled channel of a FREEDM-84A672 device. The external controller must prepend an in-band channel address to each partial packet transfer across the transmit APPI to associate the data with a channel. Detailed information on configuring the RAPI672 and the TAPI672 can be found in section 8 of this document. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 8 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 4 INTERRUPT ARCHITECTURE This section provides an overview of the FREEDM-84A672 interrupt architecture. Detailed information on the individual interrupts is available in the Longform Datasheet[1]. 4.1 Non-SBI Interrupts The FREEDM-84A672 provides a number of individual interrupts which are identified as 'I' bits within the FREEDM-84A672 Master Interrupt Status (0x008) register. When an interrupt source becomes active, the 'I' bit is set and remains set until the FREEDM-84A672 Master Interrupt Status (0x008) register is read. The FREEDM-84A672 provides interrupts to the microprocessor bus via the INTB pin of the FREEDM-84A672. The INTB pin is gated by the FREEDM84A672 Master Interrupt Enable (0x004) register. This register contains 'E' bits which can mask the 'I' bit from causing an interrupt on the INTB pin of the FREEDM-84A672. When the 'E' and 'I' bits of an interrupt source are both high, then the INTB pin is active. When the 'E' bit is low, the interrupt source will not activate the INTB pin regardless of the 'I' bit status. However, the `I' bit remains valid when interrupts are disabled and may be polled to detect the various events. The complete list of 'I' bits and 'E' bits for non-SBI interrupts is shown below: `E' Bit RFCSEE RABRTE RPFEE RFOVRE TPRTYE TUNPVE TFOVRE TFUDRE `I' Bit RFCSEI RABRTI RPFEI RFOVRI TPRTYI TUNPVI TFOVRI TFUDRI Description Receive FCS Error Receive Abort Receive Packet Format Error Receive FIFO Overrun Error Transmit Parity Error Transmit Unprovisioned Error Transmit FIFO Overflow Error Transmit FIFO Underflow Error 4.2 SBI Interrupts In addition to the interrupts described in section 4.1, interrupts can be provided to the microprocessor by the SBI Extract block of the FREEDM-84A672. The SBI Extracter interrupt status bit (SBIEXTI) of the FREEDM-84A672 Master SBI Interrupt Status (0x02C) register reports an error condition from the SBI PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 9 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Extract block to the microprocessor. Reading this register acknowledges and clears the interrupt. The SBI Extracter interrupt enable bit (SBIEXTE) of the FREEDM-84A672 Master SBI Interrupt Enable (0x028) register can mask the SBIEXTI bit from causing an interrupt on the INTB pin. When the SBIEXTE and SBIEXTI pins are both high, then the INTB pin is active. When the SBIEXTE is low, the interrupt source will not activate the INTB pin, regardless of the SBIEXTI status. However, SBIEXTI remains valid when interrupts are disabled and may be polled to detect SBI Extract block error conditions. SBI Extract Parity Error Interrupt In the FREEDM-84A672, the only error condition which the SBI Extract block reports is a parity error on the SBI DROP BUS. The PERRI bit of the SBI EXTRACT Parity Error Interrupt Reason (0x5DC) register indicates that an SBI parity error has been detected. Reading this register clears this bit. The TRIB[4:0] and SPE[1:0] fields of this register specify the SBI tributary for which a parity error was detected, and are only valid when PERRI is set. The SBI_PERR_EN bit of the SBI EXTRACT Control (0x5C0) register enables or disables SBI Parity Error Interrupts. When SBI_PERR_EN is low, SBI Parity Error Interrupts are disabled. When SBI_PERR_EN is high, SBI Parity Error Interrupts are enabled. In both cases, the SBI EXTRACT Parity Error Interrupt Reason (0x5DC) register is updated when a parity error occurs. Note: Even if SBI_PERR_EN and PERRI are both high (causing SBIEXTI to report an error condition), SBIEXTE must also be high for the SBI Extract block to cause an interrupt on the INTB pin. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 10 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 5 CONFIGURING THE SBI INTERFACE The Scaleable Bandwidth Interconnect (SBI) is a synchronous, time-division multiplexed bus designed to transfer, in a pin-efficient manner, data belonging to a number of independently timed links of varying bandwidth. The bus is timed to a reference 19.44MHz clock and a 2kHz or 166.7Hz frame pulse. All sources and sinks of data on the bus are timed to the reference clock and frame pulse. The SBI multiplexing structure is modeled on the SONET/SDH standards. The SONET/SDH virtual tributary structure is used to carry T1/J1 and E1 links. Unchannelised DS3 payloads follow a byte synchronous structure modeled on the SONET/SDH format. The multiplexed links are separated into three Synchronous Payload Envelopes (SPEs). Each envelope may be configured independently to carry up to 28 T1/J1s, 21 E1s or a DS3. Full details of the operation of the SBI interface are provided in the SBI Compatibility Specification [3]. 5.1 Configuring the SBI DROP BUS The SBI DROP BUS is a byte wide serial bus which drops SBI tributaries from multiple PHY devices to multiple link layer devices such as the FREEDM84A672. The SBI DROP BUS is configured by programming bits within the FREEDM84A672 SBI DROP BUS Master Configuration (0x048) register. The default configuration is as follows: Bit SPE1_TYP[1:0] SPE2_TYP[1:0] SPE3_TYP[1:0] Register FREEDM-84A672 SBI DROP BUS Master Configuration (0x048) FREEDM-84A672 SBI DROP BUS Master Configuration (0x048) FREEDM-84A672 SBI DROP BUS Master Configuration (0x048) Value 00 00 00 00 00 FCLK_FREQ[1:0] FREEDM-84A672 SBI DROP BUS Master Configuration (0x048) Reserved[1:0] FREEDM-84A672 SBI DROP BUS Master Configuration (0x048) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 11 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE The default indicates that all three Synchronous Payload Envelopes conveyed on the SBI DROP BUS are configured for 28 T1/J1 links and the FASTCLK input operates at a frequency of 51.84 MHz. SPE Type on the SBI DROP BUS The SPE type bits (SPEn_TYP[1:0]) determine the configuration of each of the three Synchronous Payload Envelopes conveyed on the SBI DROP BUS, according to the following table. SPEn_TYP[1:0] 00 01 10 11 FASTCLK Frequency Link Configuration 28 T1/J1 links 21 E1 links Single DS-3 link Reserved The high-speed reference clock signal (FASTCLK) is used by the FREEDM84A672 to generate an internal clock for use when processing DS-3 links. The FASTCLK frequency selector bits (FCLK_FREQ[1:0]) must be set according to the following table, depending on the frequency chosen for the FASTCLK input. FCLK_FREQ[1:0] 00 01 10 11 5.2 Configuring the SBI ADD BUS FASTCLK Frequency 51.84 MHz 44.928 MHz Reserved 66 MHz The SBI ADD BUS is a byte wide serial bus which aggregates TDM tributaries from multiple link layer devices such as the FREEDM-84A672 to multiple PHY devices. The SBI ADD BUS is configured by programming bits within the FREEDM84A672 SBI ADD BUS Master Configuration (0x04C) register. The default configuration is as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 12 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Bit SPE1_TYP[1:0] SPE2_TYP[1:0] SPE3_TYP[1:0] Register FREEDM-84A672 SBI ADD BUS Master Configuration (0x04C) FREEDM-84A672 SBI ADD BUS Master Configuration (0x04C) FREEDM-84A672 SBI ADD BUS Master Configuration (0x04C) Value 00 00 00 00 0x00 0 FCLK_FREQ[1:0] FREEDM-84A672 SBI ADD BUS Master Configuration (0x04C) Reserved[4:0] DEFAULT_DRV FREEDM-84A672 SBI ADD BUS Master Configuration (0x04C) FREEDM-84A672 SBI ADD BUS Master Configuration (0x04C) The default indicates that all three Synchronous Payload Envelopes conveyed on the SBI ADD BUS are configured for 28 T1/J1 links, the FASTCLK input operates at a frequency of 51.84 MHz, and the FREEDM-84A672 will only drive the bus when it has data to send. SPE Type on the SBI ADD BUS The SPE type bits (SPEn_TYP[1:0]) determine the configuration of each of the three Synchronous Payload Envelopes conveyed on the SBI ADD BUS, according to the following table. SPEn_TYP[1:0] 00 01 10 11 FASTCLK Frequency Link Configuration 28 T1/J1 links 21 E1 links Single DS-3 link Reserved The high-speed reference clock signal (FASTCLK) is used by the FREEDM84A672 to generate an internal clock for use when processing DS-3 links. The FASTCLK frequency selector bits (FCLK_FREQ[1:0]) must be set according to the following table, depending on the frequency chosen for the FASTCLK input. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 13 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE FCLK_FREQ[1:0] 00 01 10 11 Default Bus Driver FASTCLK Frequency 51.84 MHz 44.928 MHz Reserved 66 MHz The Default Bus Driver selector bit (DEFAULT_DRV) enables the FREEDM84A672 device to drive the SBI ADD BUS when no other device is doing so. It is recommended that one device connected to an SBI Bus be nominated as a default driver and configured to drive the bus when no other device is doing so (when the ADETECT[1:0] inputs are both 0). This feature is configured as follows: DEFAULT_DRV 0 1 Function The FREEDM-84A672 will only drive the bus when it has data to send (and when ADETECT[1:0] are both 0). The FREEDM-84A672 will drive the bus whenever the ADETECT[1:0] inputs are both 0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 14 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 6 6.1 CONFIGURING THE SBI EXTRACTER AND INSERTER Configuring the SBI Extracter The SBI receive circuitry consists of an SBI Extract block and three SBI Parallel to Serial Converter (SBI PISO) blocks. The SBI Extract block receives data from the SBI DROP BUS and converts it to an internal parallel bus format. The received data is then converted to serial bit streams by the PISO blocks. Each PISO block processes one of the three Synchronous Payload Envelopes (SPEs) conveyed on the SBI DROP BUS. The SBI Extract block may be configured to enable or disable reception of individual tributaries within the SBI DROP bus. Individual tributaries may also be configured to operate in framed or unframed mode. Each PISO block inputs data related to one SPE from the internal parallel bus and generates either 28 serial data streams at T1/J1 rate, 21 streams at E1 rate or a single stream at DS-3 rate. These serial streams are then processed by the Receive Channel Assigner block. 6.1.1 SBI EXTRACT Control The SBI Extract block is controlled by programming bits within the SBI EXTRACT Control (0x5C0) register. The default configuration is as follows: Bit SBI_PAR_CTL Reserved[2:0] Reserved[3] Register SBI EXTRACT Control (0x5C0) SBI EXTRACT Control (0x5C0) SBI EXTRACT Control (0x5C0) Value 1 0 000 0 SBI_PERR_EN SBI EXTRACT Control (0x5C0) The default indicates that odd parity mode is used for checking the SBI parity signal, and that the SBI Parity Error interrupts are disabled. SBI Parity Mode The SBI_PAR_CTL bit is used to configure the Parity mode for checking of the SBI parity signal, DDP as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 15 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE SBI_PAR_CTL 0 1 Even parity checking. Odd parity checking. Function SBI Parity Error Interrupt Enable The SBI_PERR_EN bit is used to enable SBI parity error interrupt generation and is decoded in the following table. Please see section 4.2 for more information on the SBI parity error interrupt. SBI_PERR_EN 0 1 Function SBI parity error interrupts are disabled. SBI parity error interrupts are enabled. 6.1.2 SBI EXTRACT Tributary Configuration SBI EXTRACT tributary configuration information is read from and written to the SBI EXTRACT tributary control configuration RAM. An SBI tributary in the receive direction is configured using the following procedure: 1. Poll the BUSY bit of the SBI EXTRACT Tributary RAM Indirect Access Control (0x5D0) register until it is zero. This ensures that a previous indirect RAM access has completed and a new indirect RAM access can be started. 2. The TRIB[4:0] and SPE[1:0] fields of the SBI EXTRACT Tributary RAM Indirect Access Address (0x5CC) register are used to specify which SBI tributary the control configuration RAM write or read operation will apply to. Legal values for TRIB[4:0] are b'00001' through b`11100'. Legal values for SPE[1:0] are b'01' through b`11'. Write this register as follows: Bit TRIB[4:0] SPE[1:0] Reserved Register SBI EXTRACT Tributary RAM Indirect Access Address (0x5CC) SBI EXTRACT Tributary RAM Indirect Access Address (0x5CC) SBI EXTRACT Tributary RAM Indirect Access Address (0x5CC) Value See above See above 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 16 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 3. The ENBL bit of the SBI EXTRACT Tributary RAM Indirect Access Data (0x5D8) register is used to enable the tributary. Writing to the tributary control configuration RAM with the ENBL bit set enables the SBI EXTRACT block to take tributary data from an SBI tributary and output that data to the SBI PISO blocks. The TRIB_TYP[1:0] field of the SBI EXTRACT Tributary RAM Indirect Access Data (0x5D8) register is used to configure the tributary to operate in framed or unframed mode as follows: TRIB_TYP[1:0] Tributary type 00 Reserved 01 Framed 10 Unframed 11 Reserved Specify the configuration data to be written to the tributary control configuration RAM by writing the following register: Bit ENBL Reserved[0] TRIB_TYP[1:0] Reserved[3:1] Register SBI EXTRACT Tributary RAM Indirect Access Data (0x5D8) SBI EXTRACT Tributary RAM Indirect Access Data (0x5D8) SBI EXTRACT Tributary RAM Indirect Access Data (0x5D8) SBI EXTRACT Tributary RAM Indirect Access Data (0x5D8) Value See above 0 See above 000 4. Trigger an indirect write operation on the tributary control configuration RAM by writing the following register: Bit Reserved RWB BUSY Register SBI EXTRACT Tributary RAM Indirect Access Control (0x5D0) SBI EXTRACT Tributary RAM Indirect Access Control (0x5D0) SBI EXTRACT Tributary RAM Indirect Access Control (0x5D0) Value 0 0 X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 17 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 6.2 Configuring the SBI Inserter The SBI transmit circuitry consists of an SBI Insert block and three SBI Serial to Parallel Converter (SBI SIPO) blocks. Each SIPO block processes data for one of the three Synchronous Payload Envelopes (SPEs) conveyed on the SBI ADD BUS. It receives serial data on either 28 links running at T1/J1 rate, 21 links at E1 rate or a single link at DS-3 rate and converts it to an internal parallel bus format. The SBI Insert block receives data from the SIPO blocks in the internal format and transmits it on the SBI ADD BUS. The SIPO blocks generate the serial clocks for the TCAS672 and thus are able to control the rate at which data is transmitted on to the SBI. The SBI Insert block can command the SIPO blocks to speed up or slow down these clocks in response to justification requests received on the SBI interface. This feature is controlled by the CLK_MSTR bit which is explained in section 6.2.2. The SBI Insert block also contains FIFO circuitry to compensate for short term variations in the rate at which data is output by the TCAS672 and the rate at which it is transmitted on the SBI ADD BUS. The SBI Insert block may be configured to enable or disable transmission of individual tributaries on to the SBI ADD bus. Individual tributaries may also be configured to operate in framed or unframed mode. 6.2.1 SBI INSERT Control The SBI Insert block is controlled by programming bits within the SBI INSERT Control (0x680) register. The default configuration is as follows: Bit SBI_PAR_CTL Reserved[2:0] Reserved[3] Register SBI INSERT Control (0x680) SBI INSERT Control (0x680) SBI INSERT Control (0x680) Value 1 000 0 The default indicates that the odd parity mode is used for generating the SBI parity signal. SBI Parity Mode The SBI_PAR_CTL bit is used to configure the Parity mode for generation of the SBI parity signal, ADP as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 18 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE SBI_PAR_CTL 0 1 Even parity generation. Odd parity generation. Function 6.2.2 SBI INSERT Tributary Configuration SBI INSERT tributary configuration information is read from and written to the SBI INSERT tributary control configuration RAM. An SBI tributary in the transmit direction is configured using the following procedure: 1. Poll the BUSY bit of the SBI INSERT Tributary RAM Indirect Access Control (0x690) register until it is zero. This ensures that a previous indirect RAM access has completed and a new indirect RAM access can be started. 2. The TRIB[4:0] and SPE[1:0] fields of the SBI INSERT Tributary RAM Indirect Access Address (0x68C) register are used to specify which SBI tributary the control configuration RAM write or read operation will apply to. Legal values for TRIB[4:0] are b'00001' through b`11100'. Legal values for SPE[1:0] are b'01' through b`11'. Write this register as follows: Bit TRIB[4:0] SPE[1:0] Reserved Register SBI INSERT Tributary RAM Indirect Access Address (0x68C) SBI INSERT Tributary RAM Indirect Access Address (0x68C) SBI INSERT Tributary RAM Indirect Access Address (0x68C) Value See above See above 0 3. The ENBL bit of the SBI INSERT Tributary RAM Indirect Access Data (0x698) register is used to enable the tributary. Writing to the tributary control configuration RAM with the ENBL bit set enables the SBI INSERT block to output tributary data on an SBI tributary. The TRIB_TYP[1:0] field of the SBI INSERT Tributary RAM Indirect Access Data (0x698) register is used to configure the tributary to operate in framed or unframed mode as follows: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 19 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE TRIB_TYP[1:0] 00 01 10 11 Tributary type Reserved Framed Unframed Reserved The CLK_MSTR bit of the SBI INSERT Tributary RAM Indirect Access Data (0x698) register configures the SBI tributary to operate as a timing master or slave. Setting CLK_MSTR to 1 configures the tributary as a timing master (AJUST_REQ input ignored). Setting CLK_MSTR to 0 configures the tributary as a timing slave (requests on AJUST_REQ honoured). Specify the configuration data to be written to the tributary control configuration RAM by writing the following register: Bit ENBL Reserved TRIB_TYP[1:0] CLK_MSTR Register SBI INSERT Tributary RAM Indirect Access Data (0x698) SBI INSERT Tributary RAM Indirect Access Data (0x698) SBI INSERT Tributary RAM Indirect Access Data (0x698) SBI INSERT Tributary RAM Indirect Access Data (0x698) Value See above 0 See above See above 4. Trigger an indirect write operation on the tributary control configuration RAM by writing the following register: Bit Reserved RWB BUSY Register SBI INSERT Tributary RAM Indirect Access Control (0x690) SBI INSERT Tributary RAM Indirect Access Control (0x690) SBI INSERT Tributary RAM Indirect Access Control (0x690) Value 0 0 X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 20 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 7 CONFIGURING THE SERIAL LINKS Each of the 84 bi-directional links is controlled via the RCAS672 and the TCAS672 blocks of the FREEDM-84A672. The RCAS672 controls the receive data stream while the TCAS672 controls the transmit data stream. The Receive Channel Assigner (RCAS672) The Receive Channel Assigner block processes up to 84 serial links. When receiving data from the SBI PISO blocks, links may be configured to support channelised T1/J1/E1 traffic, unchannelised DS-3 traffic or unframed traffic at T1/J1, E1 or DS-3 rates. When receiving data from the RCLK/RD inputs, links 0, 1 and 2 support unchannelised data at arbitary rates up to 52 Mbps. Each link is independent and has its own associated clock. For each link, the RCAS672 performs a serial to parallel conversion to form data bytes. The data bytes are multiplexed, in byte serial format, for delivery to the Receive HDLC Processor / Partial Packet Buffer block (RHDL672) at SYSCLK rate. In the event where multiple streams have accumulated a byte of data, multiplexing is performed on a fixed priority basis with link #0 having the highest priority and link #83 the lowest. The 84 RCAS links have a fixed relationship to the SPE and tributary numbers on the SBI DROP BUS as shown in the following table. SBI SPE No. 1 1 1 1 1 1 1 1 1 1 SBI Trib. No. 1 2 3 4 5 6 7 8 9 10 RCAS Link No. 0 3 6 9 12 15 18 21 24 27 SBI SPE No. 2 2 2 2 2 2 2 2 2 2 SBI Trib. No. 1 2 3 4 5 6 7 8 9 10 RCAS Link No. 1 4 7 10 13 16 19 22 25 28 SBI SPE No. 3 3 3 3 3 3 3 3 3 3 SBI Trib. No. 1 2 3 4 5 6 7 8 9 10 RCAS Link No. 2 5 8 11 14 17 20 23 26 29 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 21 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE SBI SPE No. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SBI Trib. No. 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 RCAS Link No. 30 33 36 39 42 45 48 51 54 57 60 63 66 69 72 75 78 81 SBI SPE No. 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 SBI Trib. No. 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 RCAS Link No. 31 34 37 40 43 46 49 52 55 58 61 64 67 70 73 76 79 82 SBI SPE No. 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 SBI Trib. No. 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 RCAS Link No. 32 35 38 41 44 47 50 53 56 59 62 65 68 71 74 77 80 83 Links containing a T1/J1 or an E1 stream may be channelised. Data at each time-slot may be independently assigned to a different channel. The RCAS672 performs a table lookup to associate the link and time-slot identity with a channel. The position of T1/J1 and E1 framing bits/bytes is identified by frame pulse signals generated by the SBI PISO blocks. Links containing a DS-3 stream are unchannelised, i.e. all data on the link belongs to one channel. The RCAS672 performs a table lookup using only the link number to determine the associated channel, as time-slots are non-existent in unchannelised links. Links may additionally be configured to operate in an unframed "clear channel" mode, in which all bit positions, including those normally reserved for framing information, are assumed to be carrying HDLC data. Links configured in unframed mode operate as unchannelised regardless of link rate and the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 22 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE RCAS672 performs a table lookup using only the link number to determine the associated channel. The Transmit Channel Assigner (TCAS672) The Transmit Channel Assigner block processes up to 672 channels. Data for all channels is sourced from a single byte-serial stream from the Transmit HDLC Controller / Partial Packet Buffer block (THDL672). The TCAS672 demultiplexes the data and assigns each byte to any one of 84 links. When sending data to the SBI SIPO blocks, each link may be configured to support channelised T1/J1/E1 traffic, unchannelised DS-3 traffic or unframed traffic at T1/J1, E1 or DS-3 rates. When sending data to the TD outputs, links 0, 1 and 2 support unchannelised data at arbitary rates up to 52 Mbps. Each link is independent and has its own associated clock. The 84 TCAS links have a fixed relationship to the SPE and tributary numbers on the SBI ADD BUS as shown in the following table. SBI SPE No. 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SBI Trib. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TCAS Link No. 0 3 6 9 12 15 18 21 24 27 30 33 36 39 42 45 SBI SPE No. 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 SBI Trib. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TCAS Link No. 1 4 7 10 13 16 19 22 25 28 31 34 37 40 43 46 SBI SPE No. 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 SBI Trib. No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 TCAS Link No. 2 5 8 11 14 17 20 23 26 29 32 35 38 41 44 47 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 23 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE SBI SPE No. 1 1 1 1 1 1 1 1 1 1 1 1 SBI Trib. No. 17 18 19 20 21 22 23 24 25 26 27 28 TCAS Link No. 48 51 54 57 60 63 66 69 72 75 78 81 SBI SPE No. 2 2 2 2 2 2 2 2 2 2 2 2 SBI Trib. No. 17 18 19 20 21 22 23 24 25 26 27 28 TCAS Link No. 49 52 55 58 61 64 67 70 73 76 79 82 SBI SPE No. 3 3 3 3 3 3 3 3 3 3 3 3 SBI Trib. No. 17 18 19 20 21 22 23 24 25 26 27 28 TCAS Link No. 50 53 56 59 62 65 68 71 74 77 80 83 As shown in the table above, TCAS links 0, 1, and 2 are mapped to tributary 1 of SPEs 1, 2 and 3 respectively. These links may be configured to operate at DS-3 rate. (They may also be configured to output data to the TD outputs at rates up to 52 Mbps.) For each of these high-speed links, the TCAS672 provides a six byte FIFO. For the remaining links (TCAS links 3 to 83, mapped to links 2 to 28 of each SPE), the TCAS672 provides a single byte holding register. The TCAS672 performs parallel to serial conversion to form bit-serial streams which are passed to the SBI SIPO blocks. In the event where multiple links are in need of data, TCAS672 requests data from upstream blocks on a fixed priority basis with link 0 having the highest priority and link 83 the lowest. Links containing a T1/J1 or an E1 stream may be channelised. Data at each time-slot may be independently assigned to be sourced from a different channel. The position of T1/J1 and E1 framing bits/bytes is identified by frame pulse signals generated by the SBI SIPO blocks. With knowledge of the transmit link and time-slot identity, the TCAS672 performs a table look-up to identify the channel from which a data byte is to be sourced. Links containing a DS-3 stream are unchannelised, in which case, all data bytes on the link belong to one channel. The TCAS672 performs a table look-up to identify the channel to which a data byte belongs using only the outgoing link identity, as no time-slots are associated with unchannelised links. Links may PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 24 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE additionally be configured to operate in an unframed "clear channel" mode, in which case the FREEDM-84A672 will output HDLC data in all bit positions, including those normally reserved for framing information. Links configured in unframed mode operate as unchannelised regardless of link rate and the TCAS672 performs a table lookup using only the link number to determine the associated channel. 7.1 SBI SPE/Tributary Links When the SPEn_EN input pin is high, the corresponding Synchronous Payload Envelope conveyed on the SBI interface is enabled and the corresponding independently timed link is disabled. This section describes the configuration of the operational and framing modes of those links mapped to SPEs on the SBI DROP and ADD buses. SBI Mode for SPEn Links The SBI mode select bits (SBI_MODE[2:0]) in the following registers configure the receive and transmit links of SPEn, where 1 n 3: Bit SBI_MODE[2:0] SBI_MODE[2:0] SBI_MODE[2:0] SBI_MODE[2:0] SBI_MODE[2:0] SBI_MODE[2:0] SPE No. 1 2 3 1 2 3 Register RCAS SBI SPE1 Configuration Register #1 (0x140) RCAS SBI SPE2 Configuration Register #1 (0x148) RCAS SBI SPE3 Configuration Register #1 (0x150) TCAS SBI SPE1 Configuration Register #1 (0x440) TCAS SBI SPE2 Configuration Register #1 (0x448) TCAS SBI SPE3 Configuration Register #1 (0x450) The encoding of the SBI_MODE[2:0] bits is shown in the following table, where 1 n 3: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 25 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE SBI_MODE [2:0] 000 001 010 011 100 101 110 111 SPEn Configuration Single unchannelised DS-3 on link n-1 28 T1/J1 links 21 E1 links (links corresponding to SPEn tributaries 22-28 are unused) Reserved Reserved Reserved Reserved Reserved Framing Mode for SPEn Links The framing mode of those links mapped to SPE 1 of the SBI DROP BUS is configured using the FEN[11:0] bits of the RCAS SBI SPE1 Configuration Register #1 (0x140) and the FEN[27:12] bits of the RCAS SBI SPE1 Configuration Register #2 (0x144). Each FEN bit, FEN[n], configures link 3n for framed operation. In unframed operation (FEN[n] = 0), all framing bit locations are treated as containing data. In framed mode (FEN[n] = 1), the contents of framing bit locations are ignored. The framing mode of those links mapped to SPE 2 of the SBI DROP BUS is configured using the FEN[11:0] bits of the RCAS SBI SPE2 Configuration Register #1 (0x148) and the FEN[27:12] bits of the RCAS SBI SPE2 Configuration Register #2 (0x14C). Each FEN bit, FEN[n], configures link 3n+1 for framed operation. In unframed operation (FEN[n] = 0), all framing bit locations are treated as containing data. In framed mode (FEN[n] = 1), the contents of framing bit locations are ignored. The framing mode of those links mapped to SPE 3 of the SBI DROP BUS is configured using the FEN[11:0] bits of the RCAS SBI SPE3 Configuration Register #1 (0x150) and the FEN[27:12] bits of the RCAS SBI SPE3 Configuration Register #2 (0x154). Each FEN bit, FEN[n], configures link 3n+2 for framed operation. In unframed operation (FEN[n] = 0), all framing bit locations are treated as containing data. In framed mode (FEN[n] = 1), the contents of framing bit locations are ignored. The framing mode of those links mapped to SPE 1 of the SBI ADD BUS is configured using the FEN[11:0] bits of the TCAS SBI SPE1 Configuration Register #1 (0x440) and the FEN[27:12] bits of the TCAS SBI SPE1 Configuration Register #2 (0x444). Each FEN bit, FEN[n], configures link 3n for framed operation. In unframed operation (FEN[n] = 0), HDLC data is PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 26 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE transmitted in all framing bit locations. In framed mode (FEN[n] = 1), the framing bit locations are unused. The framing mode of those links mapped to SPE 2 of the SBI ADD BUS is configured using the FEN[11:0] bits of the TCAS SBI SPE2 Configuration Register #1 (0x448) and the FEN[27:12] bits of the TCAS SBI SPE2 Configuration Register #2 (0x44C). Each FEN bit, FEN[n], configures link 3n+1 for framed operation. In unframed operation (FEN[n] = 0), HDLC data is transmitted in all framing bit locations. In framed mode (FEN[n] = 1), the framing bit locations are unused. The framing mode of those links mapped to SPE 3 of the SBI ADD BUS is configured using the FEN[11:0] bits of the TCAS SBI SPE3 Configuration Register #1 (0x450) and the FEN[27:12] bits of the TCAS SBI SPE3 Configuration Register #2 (0x454). Each FEN bit, FEN[n], configures link 3n+2 for framed operation. In unframed operation (FEN[n] = 0), HDLC data is transmitted in all framing bit locations. In framed mode (FEN[n] = 1), the framing bit locations are unused. Idle Time-Slot Fill Data The fill data bits (FDATA[7:0]) of the TCAS Idle Time-slot Fill Data (0x40C) register are transmitted during disabled time-slots of a channelised link (when the PROV bit of the TCAS Indirect Channel Data (0x404) register is low). The default value of FDATA[7:0] is 0xFF. 7.2 Clock/Data Links When the SPEn_EN input pin is low, the corresponding Synchronous Payload Envelope conveyed on the SBI interface is unused and the corresponding independently timed link (signals RCLK[n-1], RD[n-1], TCLK[n-1] and TD[n-1]) is enabled, where 1 n 3. The timing relationship of the receive clock (RCLK[n]) and data (RD[n]) signals is shown in Figure 2, where 0 n 2. The receive data is viewed as a contiguous serial stream. There is no concept of time-slots or framing. Every eight bits are grouped together into a byte with arbitrary alignment. The first bit received (B1 in Figure 2) is deemed the most significant bit of an octet. The last bit received (B8) is deemed the least significant bit. Bits that are to be processed by the FREEDM-84A672 are clocked in on the rising edge of RCLK[n]. Bits that should be ignored (X in Figure 2) are squelched by holding RCLK[n] quiescent. In Figure 2, the quiescent period is shown to be a low level on RCLK[n]. A high level, effected by extending the high phase of the previous valid bit, is also PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 27 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE acceptable. Selection of bits for processing is arbitrary and is not subject to any byte alignment nor frame boundary considerations. Figure 2 - Receive Link Timing RCLK[n] RD[n] B1 B2 B3 B4 X B5 X X X B6 B7 B8 B1 X The timing relationship of the transmit clock (TCLK[n]) and data (TD[n]) signals is shown in Figure 3, where 0 n 2. The transmit data is viewed as a contiguous serial stream. There is no concept of time-slots or framing. Every eight bits are grouped together into a byte with arbitrary byte alignment. Octet data is transmitted from most significant bit (B1 in Figure 3) and ending with the least significant bit (B8 in Figure 3). Bits are updated on the falling edge of TCLK[n]. A transmit link may be stalled by holding the corresponding TCLK[n] quiescent. In Figure 3, bits B5 and B2 are shown to be stalled for one cycle while bit B6 is shown to be stalled for three cycles. In Figure 3, the quiescent period is shown to be a low level on TCLK[n]. A high level, effected by extending the high phase of the previous valid bit, is also acceptable. Gapping of TCLK[n] can occur arbitrarily without regard to byte nor frame boundaries. Figure 3 - Transmit Link Timing TCLK[n] TD[n] B1 B2 B3 B4 B5 B6 B7 B8 B1 B2 The following registers control the operation of receive links #0 to #2 when they are configured to receive data from the RD[2:0] inputs (i.e. SPEn_EN input pin is low). Since the only mode of operation of the clock/data links is unchannelised mode, no additional configuration is necessary. However, the programmer must ensure that the reserved bits in the following RCAS672 and TCAS672 registers are set low for correct operation of the FREEDM-84A672. Bit Reserved[2:0] Reserved[3] Register RCAS Links #0 to #2 Configuration (0x180 - 0x188) RCAS Links #0 to #2 Configuration (0x180 - 0x188) Value 000 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 28 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Bit Reserved[2:0] Reserved[3] Register TCAS Links #0 to #2 Configuration (0x480 - 0x488) TCAS Links #0 to #2 Configuration (0x480 - 0x488) Value 000 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 29 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 8 CONFIGURING THE ANY-PHY PACKET INTERFACE The RAPI672 and TAPI672 blocks must be configured via the normal mode registers in order to enable the transferring of data between the partial packet buffers and the receive and transmit APPI. 8.1 Configuring the Receive Any-PHY Packet Interface (RAPI672) The RAPI672 is configured by programming bits within the RAPI Control (0x580) register. The values programmed affect all receive channels. The default configuration is as follows: Bit BADDR[2:0] ALL1ENB Reserved STATEN ENABLE Register RAPI Control (0x580) RAPI Control (0x580) RAPI Control (0x580) RAPI Control (0x580) RAPI Control (0x580) Value 111 1 0 0 0 The default indicates that the RAPI672 is disabled from responding to device selection. Activation of the RAPI672 By default, the RAPI672 is disabled from responding to device selection. The ENABLE bit must be set to enable normal operation of the RAPI672. The encoding of this bit is: ENABLE 0 1 Function The RAPI672 will not respond to device selection. The RAPI672 operates normally, and will respond to device selection. Base Address of the Receive APPI The base address bits (BADDR[2:0]) configure the address space occupied by the FREEDM-84A672 device for purposes of responding to receive polling and receive device selection. During polling, the BADDR[2:0] bits are used to respond to polling via the RXADDR[2:0] pins. During device selection, the PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 30 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE BADDR[2:0] are used to select a FREEDM-84A672 device, enabling it to accept data on the receive APPI. During data transfer, the RXDATA[15:13] pins of the prepended channel address reflect the BADDR[2:0] bits. All Ones Enable The All Ones Enable bit (ALL1ENB) permits the FREEDM-84A672 to respond to receive polling and device selection when BADDR[2:0] = `111'. The encoding of this bit is: ALL1ENB 0 1 Function The FREEDM-84A672 responds to receive polling and device selection when BADDR[2:0] = RXADDR[2:0] = `111'. The FREEDM-84A672 regards the all-ones address as a null address and does not respond to receive polling and device selection when BADDR[2:0] = `111', regardless of the value of RXADDR[2:0]. Status Enable The FREEDM-84A672 can be programmed to overwrite the receive data signal pins, RXDATA[7:0], of the final word of each packet transfer (REOP pin is high) with the status of packet reception when that packet is errored (RERR pin is high). The RAPI672 Status Enable bit enables this feature as follows: STATEN 0 1 Function The RAPI672 does not report detailed status information for an errored packet. The RAPI672 overwrites RXDATA[7:0] of the final word of an errored packet with status information for that packet. When STATEN = 1 and the REOP and RERR pins are both high, the status information is bit mapped on RXDATA[7:0] as follows: Bit RXDATA[0] = 1 RXDATA[1] = 1 RXDATA[2] = 1 RXDATA[3] = 1 Channel FIFO overrun Maximum packet length violation FCS error Non-octet aligned Status PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 31 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Bit RXDATA[4] = 1 RXDATA[7:5] = XH 8.2 HDLC packet abort Reserved Status Configuring the Transmit Any-PHY Packet Interface (TAPI672) The TAPI672 is configured by programming bits within the TAPI Control (0x600) register. The values programmed affect all transmit channels. The default configuration is as follows: Bit BADDR[2:0] ALL1ENB Reserved[1:0] ENABLE BLEN[7:0] Register TAPI Control (0x600) TAPI Control (0x600) TAPI Control (0x600) TAPI Control (0x600) TAPI Indirect Channel Data Register (0x608) Value 111 1 00 0 0x00 The default indicates that data provided to the TAPI672 by the transmit APPI will be ignored. Activation of the TAPI672 By default, data provided to the TAPI672 by the transmit APPI is ignored. The ENABLE bit must be set to enable normal operation of the TAPI672. The encoding of this bit is: ENABLE 0 Function The state machines in the TAPI672 are held in their idle state. The TAPI672 will complete the current data transfer and will respond to any further transactions on the transmit APPI normally (by setting TRDY high), but data provided will be ignored. The TAPI672 operates normally. Data can be transferred from the transmit APPI to the partial packet buffer in the THDL672. 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 32 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Base Address of the Receive APPI The base address bits (BADDR[2:0]) configure the address space occupied by the FREEDM-84A672 device for purposes of responding to transmit polling and transmit data transfers. During polling, the TXADDR[12:10] pins are compared with the BADDR[2:0] bits to determine if the poll address identified by TXADDR[9:0] is intended for a channel in this FREEDM-84A672 device. During data transmission, the TXDATA[15:13] pins of the prepended channel address are compared with the BADDR[2:0] bits to determine if the data to follow is intended for this FREEDM-84A672 device. All Ones Enable The All Ones Enable bit (ALL1ENB) permits the FREEDM-84A672 to respond to transmit polling and device selection when BADDR[2:0] = `111'. The encoding of this bit is: ALL1ENB 0 Function The FREEDM-84A672 responds to transmit polling when BADDR[2:0] = TXADDR[12:10] = `111' and device selection when BADDR[2:0] = TXDATA[15:13] = `111'. The FREEDM-84A672 regards the all-ones address as a null address and does not respond to transmit polling and device selection when BADDR[2:0] = `111', regardless of the values of TXADDR[12:10] and TXDATA[15:13]. 1 Channel Burst Length The channel burst length (BLEN[7:0]) bits report the data transfer burst length read from the TAPI672 channel provision RAM after an indirect read operation has completed. The data transfer burst length specifies the length (in bytes, less one) of burst data transfers on the transmit APPI which are not terminated by the assertion of TEOP. The data transfer burst length can be specified on a perchannel basis with burst lengths of up to 256 bytes. The data transfer burst length to be written to the channel provision RAM in an indirect write operation must be set up in this register before triggering the write. BLEN[7:0] reflects the value written until the completion of a subsequent indirect read operation. The BLEN[7:0] value must be set according to the indirect channel transfer size of the THDL672 block (XFER[3:0] in the THDL Indirect Channel Data #3 (0x38C) register) using the following equation: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 33 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE BLEN[7:0] = (XFER[3:0] + 1)x16 -1. A description of the XFER[3:0] bits can be found in section 9.5. The relationship between XFER[3:0] and BLEN[7:0] is shown in the following table. XFER[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 BLEN[7:0] 0x0F 0x1F 0x2F 0x3F 0x4F 0x5F 0x6F 0x7F 0x8F 0x9F 0xAF 0xBF 0xCF 0xDF 0xEF 0xFF PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 34 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 9 HDLC AND CHANNEL FIFO CONFIGURATION The FREEDM-84A672 processes the data stream in the receive direction via the RHDL672 block and it processes the data stream in the transmit direction via the THDL672 block. Each of these blocks must be configured via the Normal Mode Register Space. 9.1 Configuring the RHDL672 The RHDL672 is configured by programming bits within the RHDL Configuration (0x220) register and the RHDL Maximum Packet Length (0x224) register. The values programmed affect all receive channels. The default configuration is as follows: Bit LENCHK TSTD MAX[15:0] Register RHDL Configuration (0x220) RHDL Configuration (0x220) RHDL Maximum Packet Length (0x224) Value 0 0 0xFFFF The default indicates no maximum packet length checking and datacom bit ordering. Maximum Packet Length The RHDL672 may be configured to abort packets which exceed the maximum length of n where 0 n 0xFFFF. The following bits are written to enable or disable this feature: LENCHK 0 1 MAX[15:0] 0xFFFF n Function Receive packets are not checked for maximum size and MAX[15:0] must be set to 0xFFFF. Receive packets with total length, including address, control, information and FCS fields, greater than MAX[15:0] bytes are aborted and the remainder of the frame discarded. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 35 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Datacom/Telecom Bit Order The RHDL672 may be configured to reverse the order of bits in the HDLC data transferred across the receive APPI. The following bit is written to specify the order of bits: TSTD 0 Function Datacom standard: least significant bit of each byte on the receive APPI bus (AD[0], AD[8], AD[16], AD[24]) is the first HDLC bit received. Normally, when HDLC processing is enabled, the TSTD bit must be set to zero. Telecom standard: most significant bit of each byte on the receive APPI bus (AD[7], AD[15], AD[23], AD[31]) is the first HDLC bit received. 1 9.2 Configuring the THDL672 The THDL672 is configured by programming bits within the THDL Configuration (0x3B0) register. The values programmed affect all transmit channels. The default configuration is as follows: Bit Reserved[3:0] Reserved[4] TSTD BIT8 Register THDL Configuration (0x3B0) THDL Configuration (0x3B0) THDL Configuration (0x3B0) THDL Configuration (0x3B0) Value 0x0 0 0 0 The default indicates that data is formatted in datacom bit ordering. Datacom/Telecom Bit Order The THDL672 may be configured to reverse the order of bits in the HDLC data transferred on the transmit APPI. The following bit is written to specify the order of bits: TSTD 0 Function Datacom standard: least significant bit of each byte on the transmit APPI bus (AD[0], AD[8], AD[16], AD[24]) is the first HDLC bit transmitted. Normally, when HDLC processing is enabled, the TSTD bit must be set to zero. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 36 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE TSTD 1 Function Telecom standard: most significant bit of each byte on the transmit APPI bus (AD[7], AD[15], AD[23], AD[31]) is the first HDLC bit transmitted. BIT8 The BIT8 field affects channels of the THDL672 that are configured with 7BIT set. The BIT8 value specifies the data bit transmitted on the least significant bit of each octet. BIT8 0 1 Function Channels configured for 7BIT will transmit a zero on the least significant bit of each octet. Channels configured for 7BIT will transmit a one on the least significant bit of each octet. 9.3 Programming a Channel FIFO A Channel FIFO is created from 3 or more blocks of internal RAM, and each block holds 16 bytes of packet data. There is a total of 2048 blocks (32 Kbytes) available to assign among the receive channels, and another 2048 blocks (32 Kbytes) available to assign among the transmit channels. A FIFO is created by assigning a circular linked list of blocks as shown in Figure 4. This shows a channel FIFO consisting of 3 blocks. The quantity of buffers and the arrangement of links is chosen by the programmer, and the selection of blocks can be arbitrary. The programmer must ensure that a block is not assigned to more than one circularly linked list. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 37 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Figure 4 - Specifying a Channel FIFO Partial Packet Buffer RAM Block 0 Block 1 Block 2 Block 3 16 bytes 16 bytes 16 bytes 16 bytes Block 0 Block 1 Block 2 Block 3 Block Pointer RAM XXXH BPTR[10:0] = 0x003 XXXH BPTR[10:0] = 0x0C8 Block 200 16 bytes Block 200 BPTR[10:0] = 0x001 Block 2047 16 bytes Block 2047 XXXH 9.3.1 Receive Channel FIFO A receive channel FIFO is programmed by repeating the following procedure for each block within the circularly linked list: 1. Poll the BUSY bit of the RHDL Indirect Block Select (0x210) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 2. Write the following register with the next block in the circular linked list, or exit if all links have been programmed: Bit BPTR[10:0] Register RHDL Indirect Block Data (0x214) Value 0 through 0x7FF are valid 0 Reserved RHDL Indirect Block Data (0x214) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 38 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 3. Specify the block and update the internal block pointer RAM by writing the following register. Proceed to step 1. Bit BLOCK[10:0] Register RHDL Indirect Block Select (0x210) Value 0 through 0x7FF are valid 0 0 X Reserved BRWB BUSY RHDL Indirect Block Select (0x210) RHDL Indirect Block Select (0x210) RHDL Indirect Block Select (0x210) 9.3.2 Transmit Channel FIFO A transmit channel FIFO is programmed by repeating the following procedure for each block within the circularly linked list: 1. Poll the BUSY bit of the THDL Indirect Block Select (0x3A0) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 2. Write the following register with the next block in the circular linked list, or exit if all links have been programmed: Bit BPTR[10:0] Register THDL Indirect Block Data (0x3A4) Value 0 through 0x7FF are valid 0 0 Reserved[0] Reserved[1] THDL Indirect Block Data (0x3A4) THDL Indirect Block Data (0x3A4) 3. Specify the block and update the internal block pointer RAM by writing the following register. Proceed to step 1. Bit BLOCK[10:0] Register THDL Indirect Block Select (0x3A0) Value 0 through 0x7FF are valid 0 0 Reserved BRWB THDL Indirect Block Select (0x3A0) THDL Indirect Block Select (0x3A0) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 39 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Bit BUSY 9.4 Register THDL Indirect Block Select (0x3A0) Value X RHDL672 Channel Configuration The RHDL672 provides configurable options for each receive channel as identified in the following register fields: Bit DELIN STRIP XFER[3:0] OFFSET[1:0] CRC[1:0] INVERT PRIORITY 7BIT Register RHDL Indirect Channel Data Register #1 (0x204) RHDL Indirect Channel Data Register #1 (0x204) RHDL Indirect Channel Data Register #2 (0x208) RHDL Indirect Channel Data Register #2 (0x208) RHDL Indirect Channel Data Register #2 (0x208) RHDL Indirect Channel Data Register #2 (0x208) RHDL Indirect Channel Data Register #2 (0x208) RHDL Indirect Channel Data Register #2 (0x208) Note: When writing to RHDL Indirect Channel Data Register #1 (0x204), the reserved bit (bit 11) must be set low for correct operation of the FREEDM84A672. Delineation The data bits from the RCAS672 can be written directly to the Partial Packet Buffer or processed for flag sequence delineation, bit de-stuffing and CRC verification. The following bit enables or disables this feature: DELIN 0 Function Data is written to the Partial Packet Buffer without any HDLC processing (no flag sequence delineation, bit de-stuffing nor CRC verification) on the incoming stream. Data is processed for flag sequence delineation, bit destuffing and optionally, CRC verification (CRC verification depends on CRC[1:0] value). 1 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 40 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Strip FCS Bit The indirect frame check sequence discard bit (STRIP) enables the RHDL672 to remove the FCS data before writing to the channel FIFO. STRIP is ignored when DELIN is low or when CRC[1:0] = 00B. This feature is configured as follows: STRIP 0 1 Function Includes FCS data with the data stream written to the channel FIFO. Removes the FCS data from the data stream written to the channel FIFO. DMA Transfer Size The indirect channel transfer size configures the amount of data transferred in each transaction. When the channel FIFO depth reaches the depth specified by XFER[3:0] or when an end-of-packet exists in the FIFO, a poll of this FREEDM84A672 device will indicate that data exists and is ready to be transferred across the receive APPI. Specifying a large transfer size may affect APPI bus access latencies for other channels. The following bits specify the channel transfer size: XFER[3:0] 0 through 15 are valid Function Specifies the data transfer size in blocks: Blocks = XFER[3:0] +1, and there are 16 bytes per block. Note: XFER[3:0] should be set such that the number of blocks transferred is at least two fewer than the total allocated to the associated channel. Insertion of Offset Bytes The RHDL672 can be configured to insert offset bytes into the data stream before writing the data stream to the channel FIFO. The offset bytes are placed before each packet and their value is undefined. The following configuration options are available: OFFSET[1:0] 00 01 10 Function RHDL672 does not insert offset bytes RHDL672 inserts 1 offset byte per packet RHDL672 inserts 2 offset bytes per packet PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 41 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE OFFSET[1:0] 11 CRC Algorithm Function RHDL672 inserts 3 offset bytes per packet The RHDL672 can perform CRC verification of the incoming data stream. The available options are as follows: CRC[1:0] X 00 01 10 11 DELIN 0 1 1 1 1 No CRC verification No CRC verification CRC-CCITT verification CRC-32 verification Reserved Function HDLC Data Inversion The INVERT bit configures the RHDL672 to logically invert the incoming HDLC stream from the RCAS672 before processing it. The bit is specified as follows: INVERT 0 1 Function HDLC stream is not inverted. HDLC stream is inverted. Specifying Receive Channel Priority All receive channels that must transfer data from their channel FIFO to packet memory contend for access to the receive APPI bus. The PRIORITY bit allows specified channels to have priority access to the receive APPI bus. The bit encoding is as follows: PRIORITY 0 1 Function This channel is serviced after channels with PRIORITY=1. This channel is serviced before channels with PRIORITY=0. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 42 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Handling of Robbed bit Signaling The 7BIT enable bit configures the RHDL672 to ignore the least significant bit of each octet (last bit of each octet received) in the incoming channel stream. This bit is encoded as follows: 7BIT 0 1 Function The entire receive data stream is processed. The least significant bit (last bit of each octet received) is ignored. 9.5 THDL672 Channel Configuration The THDL672 provides configurable options for each transmit channel as identified in the following register fields: Bit DELIN CRC[1:0] FLEN[10:0] DFCS INVERT 7BIT XFER[3:0] FLAG[2:0] LEVEL[3:0] IDLE TRANS Register THDL Indirect Channel Data Register #1 (0x384) THDL Indirect Channel Data Register #1 (0x384) THDL Indirect Channel Data Register #2 (0x388) THDL Indirect Channel Data Register #2 (0x388) THDL Indirect Channel Data Register #2 (0x388) THDL Indirect Channel Data Register #2 (0x388) THDL Indirect Channel Data Register #3 (0x38C) THDL Indirect Channel Data Register #3 (0x38C) THDL Indirect Channel Data Register #3 (0x38C) THDL Indirect Channel Data Register #3 (0x38C) THDL Indirect Channel Data Register #3 (0x38C) Note: When writing to THDL Indirect Channel Data Register #1 (0x384), the reserved bit (bit 11) must be set low for correct operation of the FREEDM84A672. When writing to THDL Indirect Channel Data Register #2 (0x388), the reserved bit (bit 11) must be set low for correct operation of the FREEDM84A672. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 43 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Frame Delineation The transmit packet data from packet memory can be written directly to the outgoing data stream or processed for flag sequence insertion, bit stuffing and CRC generation. The following bit enables or disables this feature: DELIN 0 Function Data is written directly to the outgoing data stream without any HDLC processing (no flag sequence insertion, bit stuffing nor CRC generation). Data is processed for flag sequence insertion, bit stuffing and optionally, CRC generation (CRC generation depends on CRC[1:0] value). 1 CRC Algorithm The THDL672 can perform CRC generation on the outgoing data stream. The available options are as follows: CRC[1:0] X 00 01 10 11 DELIN 0 1 1 1 1 No CRC generation No CRC generation CRC-CCITT generation CRC-32 generation Reserved Function Channel FIFO Length The indirect FIFO length (FLEN[10:0]) is the number of blocks, less one, that is provisioned to the circular channel FIFO specified by the FPTR[10:0] block pointer. FLEN[10:0] Function 0 through 2047 Specifies the Channel FIFO size in blocks, where Blocks = are valid FLEN[10:0] + 1, and each block is 16 bytes. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 44 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Inverting the FCS The diagnose frame check sequence bit (DFCS) specifies whether the FCS field inserted into the transmit data stream is inverted. This is provided for diagnostic purposes and is programmed as follows: DFCS 0 1 Function FCS field in the outgoing HDLC stream is not inverted. FCS field in the outgoing HDLC stream is logically inverted. Robbed Bit Signaling The least significant stuff enable bit (7BIT) configures the THDL672 to stuff the least significant bit of each octet assigned to the transmit channel in the outgoing channel stream. 7BIT 0 1 Function The entire octet contains valid data and BIT8 is ignored. The least significant bit (last bit of each octet transmitted) does not contain channel data and is forced to the value configured by the BIT8 register bit. DMA Transfer Size The indirect channel transfer size specifies the amount of data that the partial packet processor requests from the TAPI672 block. When the channel FIFO free space reaches or exceeds the limit specified by XFER[3:0], the partial packet processor will inform the TAPI672 so that a poll on that channel reflects that the channel FIFO is able to accept XFER[3:0] + 1 blocks of data. Specifying a large transfer size may affect APPI bus access latencies for other channels. The following bits specify the channel transfer size: XFER[3:0] 0 through 15 are valid Function Specifies the data transfer size in blocks, where Blocks = XFER[3:0] + 1, and each block is 16 bytes. Note: To prevent lockup, the channel transfer size (XFER[3:0]) can be configured to be less than or equal to the start transmission level set by LEVEL[3:0] and TRANS. Alternatively, the channel transfer size can be set such that the total number of blocks in the logical channel FIFO minus the start transmission level is an integer multiple of the channel transfer size. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 45 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Specifying The Number of Flag or Idle Bytes Inserted Between Frames The THDL672 can be configured to insert either flag or idle bytes (8 bits of one's) into the data stream between HDLC packets. The number of these is programmed as follows: FLAG[2:0] 000 001 010 011 100 101 110 111 Interframe Time Fill The IDLE bit specifies the byte pattern inserted in the data stream between HDLC packets. IDLE 0 1 Function Flag bytes are inserted between HDLC packets. HDLC idle (all one's bit with no bit-stuffing) is inserted between HDLC packets. Minimum Number of Flag/Idle Bytes 1 flag / 0 Idle byte 2 flags / 0 idle byte 4 flags / 2 idle bytes 8 flags / 6 idle bytes 16 flags / 14 idle bytes 32 flags / 30 idle bytes 64 flags / 62 idle bytes 128 flags / 126 idle bytes Specifying the Channel FIFO's Starving Level and Start Transmit Level The HDLC processor starts transmitting a packet when the channel FIFO free space is less than or equal to the level specified in the appropriate Start Transmission Level column of the following table or when an end of a packet is stored in the channel FIFO. When the channel FIFO free space is less than or equal to than the level specified in the Starving Trigger Level column of the following table and the HDLC processor is transmitting a packet and an end of a packet is not stored in the channel FIFO, the partial packet buffer makes expedite requests to the TAPI672 to retrieve XFER[3:0] + 1 blocks of data. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 46 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE The starving trigger level and start transmission level are programmed via the LEVEL[3:0] and the TRANS field as follows: LEVEL[3:0] Starving Trigger Level 2 Blocks (32 bytes free) 3 Blocks (48 bytes free) 4 Blocks (64 bytes free) 6 Blocks (96 bytes free) 8 Blocks (128 bytes free) 12 Blocks (192 bytes free) 16 Blocks (256 bytes free) 24 Blocks (384 bytes free) 32 Blocks (512 bytes free) 48 Blocks (768 bytes free) 64 Blocks (1 Kbytes free) 96 Blocks (1.5 Kbytes free) 192 Blocks (3 Kbytes free) 384 Blocks (6 Kbytes free) 768 Blocks (12 Kbytes free) Start Transmission Level (TRANS=0) 1 Block (16 bytes free) 2 Blocks (32 bytes free) 3 Blocks (48 bytes free) 4 Blocks (64 bytes free) 6 Blocks (96 bytes free) 8 Blocks (128 bytes free) 12 Blocks (192 bytes free) 16 Blocks (256 bytes free) 24 Blocks (384 bytes free) 32 Blocks (512 bytes free) 48 Blocks (768 bytes free) 64 Blocks (1 Kbytes free) 128 Blocks (2 Kbytes free) 256 Blocks (4 Kbytes free) 512 Blocks (8 Kbytes free) Start Transmission Level (TRANS=1) 1 Block (16 bytes free) 1 Block (16 bytes free) 2 Blocks (32 bytes free) 3 Blocks (48 bytes free) 4 Blocks (64 bytes free) 6 Blocks (96 bytes free) 8 Blocks (128 bytes free) 12 Blocks (192 bytes free) 16 Blocks (256 bytes free) 24 Blocks (384 bytes free) 32 Blocks (512 bytes free) 48 Blocks (768 bytes free) 96 Blocks (1.5 Kbytes free) 192 Blocks (2 Kbytes free) 384 Blocks (4 Kbytes free) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 47 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE LEVEL[3:0] Starving Trigger Level 1536 Blocks (24 Kbytes free) Start Transmission Level (TRANS=0) 1024 Blocks (16 Kbytes free) Start Transmission Level (TRANS=1) 768 Blocks (8 Kbytes free) 1111 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 48 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 10 FREEDM-84A672 OPERATIONAL PROCEDURES 10.1 Device Identification, Location and System Resource Assignment This section describes the software interaction required to identify a FREEDM84A672 device on the APPI bus, and to map the Normal Mode Registers in the microprocessor memory map. Identifying and Locating a FREEDM-84A672 The software can identify a FREEDM-84A672 attached to an APPI bus by reading the TYPE[3:0] bits in the FREEDM-84A672 Master Reset (0x000) register. The default value of TYPE[3:0] = 0101B indicates that the device is the FREEDM-84A672 member of the FREEDM family of products. For purposes of responding to receive polling and receive device selection, the address space occupied by each FREEDM-84A672 on the receive APPI needs to be configured using the base address bits (BADDR[2:0]) in the RAPI Control (0x580) register. Similarly, for purposes of responding to transmit polling and transmit data transfers, the address space occupied by each FREEDM-84A672 on the transmit APPI needs to be configured using the base address bits (BADDR[2:0]) in the TAPI Control (0x600) register. Note that up to seven FREEDM-84A672 devices may share a single APPI bus (one address is reserved as a null address), with an external controller acting as bus master. In addition, the software can identify the version level of the FREEDM-84A672 with the ID[7:0] bits in the FREEDM-84A672 Master Reset (0x000) register. This may be useful to distinguish between future versions of the FREEDM84A672. Memory Mapping the Register Space During power-up, the Normal Mode Register space needs to be mapped to the microprocessor. This register space is located in the FREEDM-84A672 and is accessed through the microprocessor interface. All registers are 16 bits wide but are dword aligned in the microprocessor memory map. 10.2 Reset This section describes the procedure to reset the FREEDM-84A672 via software. The FREEDM-84A672 is powered on in an inactive state and should be reset via PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 49 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE software following a hardware reset, or as required by the embedded processor. The reset procedure is normally followed by the initialization procedure. The steps to reset a FREEDM-84A672 are: 1. If the FREEDM-84A672 was active before the reset procedure then the deactivation procedure must be done (see section 10.5). 2. The RESET bit in the FREEDM-84A672 Master Reset (0x000) register must be written high and then written low. This reset procedure has the following effects: * The RESET bit allows the FREEDM-84A672 to be reset under software control. If the RESET bit is a logic one, the entire FREEDM-84A672 except the microprocessor interface is held in reset. This bit is not self-clearing. Therefore, a logic zero must be written to bring the FREEDM-84A672 out of reset. Holding the FREEDM-84A672 in a reset state places it into a low power, stand-by mode. A hardware reset clears the RESET bit, thus negating the software reset. All Normal Mode registers are set to their default values. None of the channel provisioning, or the Channel FIFO configuration is preserved under software reset. * * 10.3 Initialization This section describes the procedure to initialize the FREEDM-84A672. The initialization procedure normally follows the software reset procedure and is followed by the activation procedure. The steps to initialize a FREEDM-84A672 are: 1. Configure the SBI interface, and the SBI Extracter and Inserter for the SPEs conveyed on the SBI interface. The register accesses are described in sections 5 and 6. 2. Configure the RCAS672 and TCAS672 serial links. The register accesses are described in section 7. 3. Assign base addresses for the receive and the transmit APPI. The register accesses are described in sections 8.1 and 8.2. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 50 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 4. Configure HDLC processing of the RHDL672 and the THDL672 blocks. The register accesses are described in sections 9.1 and 9.2. 10.4 Activation Procedure The activation procedure is required to place the FREEDM-84A672 in a state after which the software may service FREEDM-84A672 interrupts, provision/unprovision channels, and monitor the status of the FREEDM-84A672. The activation procedure normally follows the initialization procedure. The steps to activate a FREEDM-84A672 are: 1. Enable interrupt `E' bits, SBIEXTE and SBI_PERR_EN as described in section 4. 2. Enable data transfer across the receive and transmit APPI by setting the ENABLE bits to one in the RAPI672 and TAPI672 registers as described in sections 8.1 and 8.2. 3. The SYSCLKA, REFCLKA, FASTCLKA, C1FPA, RXCLKA, and TXCLKA bits in the FREEDM-84A672 Master Clock/Frame Pulse Activity Monitor and Accumulation Trigger (0x00C) register should be read periodically to detect for stuck at conditions. The SYSCLKA bit must be read high for proper operation of the FREEDM-84A672. A low value indicates a failure in clocking that is provided at the SYSCLK input pin of the FREEDM-84A672. Similarly, a low value in the other register bits indicates a failure in clocking that is provided by the corresponding input pin. 10.5 Deactivation Procedure The deactivation procedure is required to place the FREEDM-84A672 in a state in which it will not interrupt the embedded processor, or transfer data across the APPI. This procedure should occur after the FREEDM-84A672 actively transfers packets, or to gracefully shut down the FREEDM-84A672. The steps to deactivate a FREEDM-84A672 are: 1. Disable interrupt `E' bits, SBIEXTE and SBI_PERR_EN as described in section 4. 2. Disable data transfer across the receive and transfer APPI by programming the ENABLE bits to zero in the RAPI672 and TAPI672 registers as described in sections 8.1 and 8.2. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 51 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 3. Continue by performing the software reset procedure. 10.6 Provisioning a Channel The provisioning procedure normally follows the activation procedure and enables the FREEDM-84A672 to receive and/or transmit packets. 10.6.1 Receive Channel Provisioning The steps to provision a receive channel RCC, where 0 RCC 671 are: 1. Disable FREEDM-84A672 processing of the channel's data stream to allow for graceful provisioning. Write the following bits: Bit DCHAN[9:0] CHDIS Register RCAS Channel Disable (0x10C) RCAS Channel Disable (0x10C) Value RCC 1 2. Program the Channel FIFO as described in section 9.3.1. 3. Poll the BUSY bit of the RHDL Indirect Channel Select (0x200) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 4. Specify the HDLC configuration for this channel by writing appropriate bits in the RHDL Indirect Channel Data Register #1 (0x204) and the RHDL Indirect Channel Data Register #2 (0x208) as described in section 9.4. When writing the RHDL Indirect Channel Data Register #1 (0x204), ensure that the PROV bit is set, and ensure that the FPTR[10:0] bits identify a block within the circular linked list of buffers of step 2. 5. Specify the RHDL672 channel to provision by writing the following register. Then poll the BUSY bit to ensure that it is low before proceeding to step 6. Bit CHAN[9:0] CRWB BUSY Register RHDL Indirect Channel Select (0x200) RHDL Indirect Channel Select (0x200) RHDL Indirect Channel Select (0x200) Value RCC 0 X 6. Poll the BUSY bit of the RCAS Indirect Link and Time-slot Select (0x100) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 52 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 7. Specify the RCAS672 channel that is provisioned. Write the following register: Bit CHAN[9:0] PROV CDLBEN Register RCAS Indirect Channel Data (0x104) RCAS Indirect Channel Data (0x104) RCAS Indirect Channel Data (0x104) Value RCC 1 0 8. For a channelised link, specify the time-slots which are assigned for processing on this channel by writing the following register once for each time-slot that is assigned to the channel. Valid values for TSLOT[4:0] are 1 through 24 for a T1/J1 link, and 1 through 31 for an E1 link. For an unchannelised or unframed link, TSLOT[4:0] must only have the value 0, and this register is written just once. Each write must be followed by a read to determine whether the BUSY bit (bit15) is low, and to ensure that the indirect RAM has been updated. Bit TSLOT[4:0] LINK[6:0] Register RCAS Indirect Link and Time-slot Select (0x100) RCAS Indirect Link and Time-slot Select (0x100) RCAS Indirect Link and Time-slot Select (0x100) RCAS Indirect Link and Time-slot Select (0x100) Value see above 0 through 83 are valid 0 X RWB BUSY 9. Enable FREEDM-84A672 processing of the channel data stream to allow for graceful provisioning. Write the following bits: Bit DCHAN[9:0] CHDIS Warning: * The RCAS Channel Disable bit (CHDIS) is only applicable to one channel at a time. In other words, the receive channel provisioning procedure needs to be run once for each channel. Register RCAS Channel Disable (0x10C) RCAS Channel Disable (0x10C) Value RCC 0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 53 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE * The programmer must ensure that the channel has not been provisioned, or has been unprovisioned before doing the provisioning procedure. The reset procedure has the effect of unprovisioning all channels of the FREEDM84A672. Continuous polling of a register in a tight loop involves multiple microprocessor memory read transactions and may have an adverse effect on the microprocessor bus bandwidth available for other activities. The recommended method of polling the BUSY bit is to read the register on expiration of a system timer, or after a number of CPU clock ticks. Recommended time intervals are in the range 0.1 msec through 1 msec. A Channel is not provisioned until the BUSY bit toggles low. * * 10.6.2 Transmit Channel Provisioning The steps to provision a transmit channel TCC, where 0 TCC 671 are: 1. Disable FREEDM-84A672 processing of the channel's data stream to allow for graceful provisioning. Write the following bits: Bit DCHAN[9:0] CHDIS Register TCAS Channel Disable (0x410) TCAS Channel Disable (0x410) Value TCC 1 2. Program the Channel FIFO as described in section 9.3.2 for a transmit channel. 3. Poll the BUSY bit of the THDL Indirect Channel Select (0x380) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 4. Specify the HDLC configuration for this transmit channel by writing the THDL Indirect Channel Data Register #1 (0x384), THDL Indirect Channel Data Register #2 (0x388) and the THDL Indirect Channel Data Register #3 (0x38C) as described in section 9.5. In writing the THDL Indirect Channel Data Register #1 (0x384), ensure the PROV bit is set, and ensure the FPTR[10:0] bits identify a block within the circular linked list of buffers of step 2. 5. Specify the THDL672 channel that is provisioned by writing the following register. Then poll the BUSY bit to ensure it is low before proceeding with step 6. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 54 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Bit CHAN[9:0] CRWB BUSY Register THDL Indirect Channel Select (0x380) THDL Indirect Channel Select (0x380) THDL Indirect Channel Select (0x380) Value TCC 0 X 6. Poll the BUSY bit of the TCAS Indirect Link and Time-slot Select (0x400) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 7. Specify the TCAS672 channel that is provisioned. Write the following register: Bit CHAN[9:0] PROV Register TCAS Indirect Channel Data (0x404) TCAS Indirect Channel Data (0x404) Value TCC 1 8. For a channelised link, specify the time-slots which are assigned for processing on this channel by writing the following register once for each time-slot that is assigned to the channel. Valid values for TSLOT[4:0] are 1 through 24 for a T1/J1 link, and 1 through 31 for an E1 link. For an unchannelised or unframed link, TSLOT[4:0] must only have the value 0, and this register is written just once. Each write must be followed by a read to determine whether the BUSY bit (bit15) is low, and to ensure that the indirect RAM has been updated. Bit TSLOT[4:0] LINK[6:0] Register TCAS Indirect Link and Time-slot Select (0x400) TCAS Indirect Link and Time-slot Select (0x400) TCAS Indirect Link and Time-slot Select (0x400) TCAS Indirect Link and Time-slot Select (0x400) Value see above 0 through 83 are valid 0 X RWB BUSY 9. Poll the BUSY bit of the TAPI Indirect Channel Provisioning (0x604) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 55 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 10. Specify the channel burst length and enable channel provisioning by writing the following register. The BLEN[7:0] bits need to be set according to the XFER[3:0] value of the THDL672 as described in section 8.2. Bit BLEN[7:0] PROV Register TAPI Indirect Channel Data Register (0x608) TAPI Indirect Channel Data Register (0x608) Value see above 1 11. Specify the TAPI672 channel to provision. Write the following register fields, then poll the BUSY bit to ensure that the provisioning process has completed. Bit CHAN[9:0] RWB BUSY Register TAPI Indirect Channel Provisioning (0x604) TAPI Indirect Channel Provisioning (0x604) TAPI Indirect Channel Provisioning (0x604) Value TCC 0 X 12. Enable FREEDM-84A672 processing of the channel data stream to allow for graceful provisioning. Write the following bits: Bit DCHAN[9:0] CHDIS Warning: * The TCAS Channel Disable bit (CHDIS) is only applicable to one channel at a time. In other words, the transmit channel provisioning procedure needs to be run once for each channel. The programmer must ensure that the channel has not been provisioned, or has been unprovisioned before doing the provisioning procedure. The reset procedure has the affect of unprovisioning all channels of the FREEDM84A672. Continuous polling of a register in a tight loop involves multiple microprocessor memory read transactions and may have an adverse effect on the microprocessor bus bandwidth available for other activities. The recommended method of polling the BUSY bit is to read the register on expiration of a system timer, or after a number of CPU clock ticks. Recommended time intervals are in the range 0.1 msec through 1 msec. Register TCAS Channel Disable (0x410) TCAS Channel Disable (0x410) Value TCC 0 * * PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 56 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE * A Channel is not provisioned until the BUSY bit toggles low. 10.7 Unprovisioning a Channel The unprovisioning procedure is normally applied to channels that are provisioned. 10.7.1 Receive Channel Unprovisioning The steps to unprovision a receive channel RCC, where 0 RCC 671 are: 1. Disable FREEDM-84A672 processing of the channel's data stream to allow for graceful unprovisioning. Write the following bits: Bit DCHAN[9:0] CHDIS Register RCAS Channel Disable (0x10C) RCAS Channel Disable (0x10C) Value RCC 1 2. Poll the BUSY bit of the RCAS Indirect Link and Time-slot Select (0x100) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 3. Specify the RCAS672 channel to unprovision by writing the following register: Bit CHAN[9:0] PROV CDLBEN Register RCAS Indirect Channel Data (0x104) RCAS Indirect Channel Data (0x104) RCAS Indirect Channel Data (0x104) Value RCC 0 X 4. For a channelised link, specify the time-slots which are unassigned on this channel by writing the following register once for each time-slot that is unassigned. Valid values for TSLOT[4:0] are 1 through 24 for a T1/J1 link, and 1 through 31 for an E1 link. For an unchannelised or unframed link, TSLOT[4:0] must only have the value 0, and this register is written just once. Each write must be followed by a read to determine whether the BUSY bit (bit15) is low, and to ensure that the indirect RAM has been updated. Bit TSLOT[4:0] Register RCAS Indirect Link and Time-slot Select (0x100) Value see above PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 57 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Bit LINK[6:0] Register RCAS Indirect Link and Time-slot Select (0x100) RCAS Indirect Link and Time-slot Select (0x100) RCAS Indirect Link and Time-slot Select (0x100) Value 0 through 83 are valid 0 X RWB BUSY 5. Poll the BUSY bit of the RHDL Indirect Channel Select (0x200) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 6. Read the RHDL672 channel data by writing the following register. Then poll the BUSY bit to ensure it is low before proceeding with step 7. Bit CHAN[9:0] CRWB BUSY Register RHDL Indirect Channel Select (0x200) RHDL Indirect Channel Select (0x200) RHDL Indirect Channel Select (0x200) Value RCC 1 X 7. Read the RHDL672 indirect channel data and check that the TAVAIL bit of the RHDL Indirect Channel Data #1 (0x204) register is zero. This ensures that the last DMA transfer request for this channel has completed. If the TAVAIL bit is zero, proceed to step 8, otherwise, return to step 6. 8. Write the RHDL Indirect Channel Data #1 (0x204) register with PROV modified to zero, while keeping the same FPTR[10:0] bits. 9. Specify the RHDL672 channel to unprovision by writing the following register. Then poll the BUSY bit to ensure that it is low before proceeding with step 10. Bit CHAN[9:0] CRWB BUSY Register RHDL Indirect Channel Select (0x200) RHDL Indirect Channel Select (0x200) RHDL Indirect Channel Select (0x200) Value RCC 0 X 10. Enable FREEDM-84A672 processing of the unprovisioned channel. Write the following bits: PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 58 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Bit DCHAN[9:0] CHDIS Warning: * Register RCAS Channel Disable (0x10C) RCAS Channel Disable (0x10C) Value RCC 0 The RCAS Channel Disable bit (CHDIS) is only applicable to one channel at a time. In other words, the receive channel unprovisioning procedure needs to be run once for each channel. Continuous polling of a register in a tight loop involves multiple microprocessor memory read transactions and may have an adverse effect on the microprocessor bus bandwidth available for other activities. The recommended method of polling the BUSY bit is to read the register on expiration of a system timer, or after a number of CPU clock ticks. Recommended time intervals are in the range 0.1 msec through 1 msec. A Channel is not unprovisioned until the BUSY bit toggles low. * * 10.7.2 Transmit Channel Unprovisioning The steps to unprovision a transmit channel TCC, where 0 TCC 671 are: 1. Poll the BUSY bit of the TAPI Indirect Channel Provisioning (0x604) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 2. Enable channel unprovisioning by writing the following register: Bit PROV Register TAPI Indirect Channel Data Register (0x608) Value 0 3. Specify the TAPI672 channel to unprovision. Write the following register fields, then poll the BUSY bit to ensure that the unprovisioning process has completed. Bit CHAN[9:0] RWB BUSY Register TAPI Indirect Channel Provisioning (0x604) TAPI Indirect Channel Provisioning (0x604) TAPI Indirect Channel Provisioning (0x604) Value TCC 0 X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 59 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 4. Disable FREEDM-84A672 processing of the channel's data stream to allow for graceful unprovisioning. Write the following bits: Bit DCHAN[9:0] CHDIS Register TCAS Channel Disable (0x410) TCAS Channel Disable (0x410) Value TCC 1 5. Poll the BUSY bit of the TCAS Indirect Link and Time-slot Select (0x400) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 6. Specify the TCAS672 channel to be unprovisioned. Write the following register: Bit CHAN[9:0] PROV Register TCAS Indirect Channel Data (0x404) TCAS Indirect Channel Data (0x404) Value TCC 0 7. For a channelised link, specify the time-slots which are unassigned for processing on this channel by writing the following register once for each time-slot that is unassigned. Valid values for TSLOT[4:0] are 1 through 24 for a T1/J1 link, and 1 through 31 for an E1 link. For an unchannelised or unframed link, TSLOT[4:0] must only have the value 0, and this register is written just once. Each write must be followed by a read to determine whether the BUSY bit (bit15) is low, and to ensure that the indirect RAM has been updated. Bit TSLOT[4:0] LINK[6:0] Register TCAS Indirect Link and Time-slot Select (0x400) TCAS Indirect Link and Time-slot Select (0x400) TCAS Indirect Link and Time-slot Select (0x400) TCAS Indirect Link and Time-slot Select (0x400) Value see above 0 through 83 are valid 0 X RWB BUSY PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 60 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 8. Poll the BUSY bit of the THDL Indirect Channel Select (0x380) register until it is zero. This ensures that a previous indirect RAM access has completed and that a new indirect RAM access can be started. 9. Read the THDL672 channel data by writing the following register. Then poll the BUSY bit to ensure that it is low before proceeding with step 9. Bit CHAN[9:0] CRWB BUSY Register THDL Indirect Channel Select (0x380) THDL Indirect Channel Select (0x380) THDL Indirect Channel Select (0x380) Value TCC 1 X 10. Read the THDL Indirect Channel Data #1 (0x384) register. Then write this register with PROV modified to zero, while keeping the same FPTR[10:0] bits. 11. Specify the THDL672 channel to unprovision by writing the following register. Then poll the BUSY bit to ensure that it is low before proceeding with step 11. Bit CHAN[9:0] CRWB BUSY Register THDL Indirect Channel Select (0x380) THDL Indirect Channel Select (0x380) THDL Indirect Channel Select (0x380) Value TCC 0 X 12. Enable FREEDM-84A672 processing of the channel. Write the following bits: Bit DCHAN[9:0] CHDIS Warning: * The TCAS Channel Disable bit (CHDIS) is only applicable to one channel at a time. In other words, the transmit channel unprovisioning procedure needs to be run once for each channel. Continuous polling of a register in a tight loop involves multiple microprocessor memory read transactions and may have an adverse effect on the microprocessor bus bandwidth available for other activities. The recommended method of polling the BUSY bit is to read the register on Register TCAS Channel Disable (0x410) TCAS Channel Disable (0x410) Value TCC 0 * PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 61 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE expiration of a system timer, or after a number of CPU clock ticks. Recommended time intervals are in the range 0.1 msec through 1 msec. * A Channel is not unprovisioned until the BUSY bit toggles low. 10.8 Receive Sequence The software is not required to receive packets when interfacing to the RAPI672. Data transfer functions for the FREEDM-84A672 are performed by an external controller. In the receive direction, the external controller transfers partial packets out of the internal 32 Kbyte partial packet buffer RAM in the RHDL672, across the receive APPI bus, and into host packet memory. Please refer to the Longform Datasheet[1] for detailed information on the operation and timing of the receive APPI. 10.9 Transmit Sequence The software is not required to transmit packets when interfacing to the TAPI672. Data transfer functions for the FREEDM-84A672 are performed by an external controller. In the transmit direction, the external controller provides packets to transmit using the transmit APPI. For each provisioned HDLC channel, an external controller transfers partial packets across the transfer APPI, and into the internal 32 Kbyte partial packet buffer RAM in the THDL672. Please refer to the Longform Datasheet[1] for detailed information on the operation and timing of the transmit APPI. 10.10 Performance Counters The FREEDM-84A672 provides four count registers within the Normal Mode Register Space. These are as follows: Bit OF[15:0] UF[15:0] C1[15:0] C2[15:0] Register PMON Receive FIFO Overflow Count (0x504) PMON Transmit FIFO Underflow Count (0x508) PMON Configurable Count #1 (0x50C) PMON Configurable Count #2 (0x510) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 62 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE The software must poll these counters to prevent overflow. Figure 5 illustrates the sequence of events when the counters are polled. The PMON Status (0x500) register provides status bits which indicate whether any of the four internal holding counters has overflowed. Figure 5 - Event Sequence for Polling of Counters Accumulation Period, N-1 Accumulation Period, N Reset Counter Count Events Accumulation Period, N+1 Reset Counter Internal Counter Count Value Transfer Count Value Transfer Visible Counter Delay Reload Counter Read Counter Time (Not to Scale) The software initiates a counter reload by writing to the FREEDM-84A672 Master Clock/Frame Pulse Activity Monitor and Accumulation Trigger (0x00C) register. There is a small delay to transfer data from internal counters to the visible counters. The recommended polling strategy is to read the counters first before initiating a reload. Using this strategy, the transfer latency can be ignored. Counters are normally configured during initialization. The first configurable count register is assigned by setting one of the following register bits, while setting all other bits to zero: Bit RSPE1EN Register FREEDM-84A672 Master Performance Monitor Control (0x024) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 63 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Bit RFCSE1EN RABRT1EN RLENE1EN RP1EN TABRT1EN TP1EN Register FREEDM-84A672 Master Performance Monitor Control (0x024) FREEDM-84A672 Master Performance Monitor Control (0x024) FREEDM-84A672 Master Performance Monitor Control (0x024) FREEDM-84A672 Master Performance Monitor Control (0x024) FREEDM-84A672 Master Performance Monitor Control (0x024) FREEDM-84A672 Master Performance Monitor Control (0x024) The second configurable count register is assigned by setting one of the following register bits, while setting all other bits to zero: Bit RSPE2EN RFCSE2EN RABRT2EN RLENE2EN RP2EN TABRT2EN TP2EN Register FREEDM-84A672 Master Performance Monitor Control (0x024) FREEDM-84A672 Master Performance Monitor Control (0x024) FREEDM-84A672 Master Performance Monitor Control (0x024) FREEDM-84A672 Master Performance Monitor Control (0x024) FREEDM-84A672 Master Performance Monitor Control (0x024) FREEDM-84A672 Master Performance Monitor Control (0x024) FREEDM-84A672 Master Performance Monitor Control (0x024) PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 64 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 10.11 Line Loopback Serial links of the RCAS672/TCAS672 can be placed in line loopback. In this configuration, the data on the receive link output by the SBI PISO blocks is looped back to the transmit link input of the SBI SIPO blocks as illustrated in Figure 6. Figure 6 - Line Loopback Tx Tx Any-PHY Packet Interface (transmit data is dropped before reaching the link) Rx Serial Link Interface FREEDM-84A672 Rx Serial links can be placed in line loopback by setting the appropriate bit within one of the following registers. There are 84 bits corresponding to the 84 serial links. Bit LLBEN[15:0] LLBEN[31:16] LLBEN[47:32] LLBEN[63:48] LLBEN[79:64] LLBEN[83:80] Register FREEDM-84A672 Master Line Loopback #1 (0x030) FREEDM-84A672 Master Line Loopback #2 (0x034) FREEDM-84A672 Master Line Loopback #3 (0x038) FREEDM-84A672 Master Line Loopback #4 (0x03C) FREEDM-84A672 Master Line Loopback #5 (0x040) FREEDM-84A672 Master Line Loopback #6 (0x044) Note: The software should unprovision channels associated with the link that is placed in line loopback mode before placing the link in line loopback. This will prevent the data stream at the serial link from passing through the FREEDM84A672 to the receive APPI. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 65 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE 10.12 Diagnostic Loopback Each channel of the FREEDM-84A672 can be placed in a diagnostic loopback mode. In this configuration, the transmit data stream is looped back to the receive data stream as illustrated in Figure 7. The pair of transmit/receive channels is configured in diagnostic loopback mode by provisioning both the transmit and the receive channels as specified in section 10.6, except with the CDLBEN bit set high within the RCAS Indirect Channel Data (0x104) register. In diagnostic loopback mode, the transmit channel data is looped back as well as driven onto the transmit serial link. The channel data from the receive serial link is dropped. The bit timing for the diagnostic loopback mode is generated internally. This clock is derived from REFCLK, C1FP and FASTCLK (if the SPE is configured to support DS-3 links) so these inputs should be active. Figure 7 - Diagnostic Loopback Tx Serial Link Interface (receive channel data is dropped) Rx Tx FREEDM-84A672 Any-PHY Packet Interface Rx PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 66 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE APPENDIX A - REGISTER LEVEL CHANGES The following table is a comparison of the normal mode registers at the register level among the FREEDM-32, the FREEDM-32A672 and the FREEDM-84A672. Registers in bold indicate differences at the register level among the members of the FREEDM family listed in the table. Table entries that are "N/A" indicate that the register is not applicable in the corresponding FREEDM device. Please see Appendix E for differences at the bit level for the normal mode registers. Register FREEDM-x Master Reset FREEDM-x Master Interrupt Enable FREEDM-x Master Interrupt Status FREEDM-x Master Clock/Frame Pulse/BERT Activity Monitor and Accumulation Trigger FREEDM-x Master Link Activity Monitor FREEDM-x Master Line Loopback #1 FREEDM-x Master Line Loopback #2 Reserved FREEDM-x Reserved FREEDM-x Master BERT Control FREEDM-x Master Performance Monitor Control FREEDM-x Master SBI Interrupt Enable FREEDM-32 FREEDM-32A672 FREEDM-84A672 PCI Offset Address Address 0x000 0x004 0x008 0x00C 0x000 0x004 0x008 0x00C 0x000 0x004 0x008 0x00C 0x010 0x014 0x018 0x01C N/A 0x020 0x024 N/A 0x010 0x014 0x018 N/A 0x01C 0x020 0x024 N/A N/A 0x030 0x034 0x010 - 0x020 N/A N/A 0x024 0x028 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 67 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Register FREEDM-x Master SBI Interrupt Status FREEDM-x Master Line Loopback #3 FREEDM-x Master Line Loopback #4 FREEDM-x Master Line Loopback #5 FREEDM-x Master Line Loopback #6 FREEDM-x SBI DROP BUS Master Configuration FREEDM-x SBI ADD BUS Master Configuration Reserved GPIC Control GPIC Reserved Reserved RCAS Indirect Channel and Time-slot Select RCAS Indirect Channel Data RCAS Framing Bit Threshold RCAS Reserved RCAS Channel Disable RCAS Reserved FREEDM-32 FREEDM-32A672 FREEDM-84A672 PCI Offset Address Address N/A N/A N/A N/A N/A N/A N/A 0x028 - 0x03C 0x040 0x044 - 0x07C 0x080 - 0x0FC 0x100 0x104 0x108 N/A 0x10C 0x110 - 0x17C N/A N/A N/A N/A N/A N/A N/A 0x028 - 0x0FC N/A N/A N/A 0x100 0x104 0x108 N/A 0x10C 0x110 - 0x17C 0x02C 0x038 0x03C 0x040 0x044 0x048 0x04C 0x050 - 0x0FC N/A N/A N/A 0x100 0x104 N/A 0x108 0x10C 0x110 - 0x13C PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 68 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Register RCAS SBI SPE1 Configuration Register #1 RCAS SBI SPE1 Configuration Register #2 RCAS SBI SPE2 Configuration Register #1 RCAS SBI SPE2 Configuration Register #2 RCAS SBI SPE3 Configuration Register #1 RCAS SBI SPE3 Configuration Register #2 RCAS Reserved RCAS Links #0 through #2 Configuration RCAS Links #3 through #31 Configuration RCAS Reserved RHDL Indirect Channel Select RHDL Indirect Channel Data Register #1 RHDL Indirect Channel Data Register #2 RHDL Reserved RHDL Indirect Block Select RHDL Indirect Block Data Register RHDL Reserved RHDL Configuration FREEDM-32 FREEDM-32A672 FREEDM-84A672 PCI Offset Address Address N/A N/A N/A N/A N/A N/A N/A 0x180 - 0x188 0x18C - 0x1FC N/A 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 - 0x21C 0x220 N/A N/A N/A N/A N/A N/A N/A 0x180 - 0x188 0x18C - 0x1FC N/A 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 - 0x21C 0x220 0x140 0x144 0x148 0x14C 0x150 0x154 0x158 - 0x17C 0x180 - 0x188 N/A 0x18C - 0x1FC 0x200 0x204 0x208 0x20C 0x210 0x214 0x218 - 0x21C 0x220 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 69 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Register RHDL Maximum Packet Length RHDL Reserved Reserved RMAC Control RMAC Indirect Channel Provisioning RMAC Packet Descriptor Table Base LSW RMAC Packet Descriptor Table Base MSW RMAC Queue Base LSW RMAC Queue Base MSW RMAC Packet Descriptor Reference Large Buffer Free Queue Start RMAC Packet Descriptor Reference Large Buffer Free Queue Write RMAC Packet Descriptor Reference Large Buffer Free Queue Read RMAC Packet Descriptor Reference Large Buffer Free Queue End RMAC Packet Descriptor Reference Small Buffer Free Queue Start RMAC Packet Descriptor Reference Small Buffer Free Queue Write FREEDM-32 FREEDM-32A672 FREEDM-84A672 PCI Offset Address Address 0x224 0x228 - 0x23C 0x240 - 0x27C 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x224 0x228 - 0x23C 0x240 - 0x37C N/A N/A N/A N/A N/A N/A N/A 0x224 0x228 - 0x23C 0x240 - 0x37C N/A N/A N/A N/A N/A N/A N/A 0x29C N/A N/A 0x2A0 N/A N/A 0x2A4 N/A N/A 0x2A8 N/A N/A 0x2AC N/A N/A PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 70 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Register RMAC Packet Descriptor Reference Small Buffer Free Queue Read RMAC Packet Descriptor Reference Small Buffer Free Queue End RMAC Packet Descriptor Reference Ready Queue Start RMAC Packet Descriptor Reference Ready Queue Write RMAC Packet Descriptor Reference Ready Queue Read RMAC Packet Descriptor Reference Ready Queue End RMAC Reserved TMAC Control TMAC Indirect Channel Provisioning TMAC Descriptor Table Base LSW TMAC Descriptor Table Base MSW TMAC Queue Base LSW TMAC Queue Base MSW TMAC Descriptor Reference Free Queue Start FREEDM-32 FREEDM-32A672 FREEDM-84A672 PCI Offset Address Address 0x2B0 N/A N/A 0x2B4 N/A N/A 0x2B8 N/A N/A 0x2BC N/A N/A 0x2C0 N/A N/A 0x2C4 N/A N/A 0x2C8 - 0x2FC 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 71 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Register TMAC Descriptor Reference Free Queue Write TMAC Descriptor Reference Free Queue Read TMAC Descriptor Reference Free Queue End TMAC Descriptor Reference Ready Queue Start TMAC Descriptor Reference Ready Queue Write TMAC Descriptor Reference Ready Queue Read TMAC Descriptor Reference Ready Queue End TMAC Reserved THDL Indirect Channel Select THDL Indirect Channel Data #1 THDL Indirect Channel Data #2 THDL Indirect Channel Data #3 THDL Reserved THDL Indirect Block Select FREEDM-32 FREEDM-32A672 FREEDM-84A672 PCI Offset Address Address 0x31C N/A N/A 0x320 N/A N/A 0x324 0x328 N/A N/A N/A N/A 0x32C N/A N/A 0x330 N/A N/A 0x334 N/A N/A 0x338 - 0x37C 0x380 0x384 0x388 0x38C 0x390 - 0x39C 0x3A0 N/A 0x380 0x384 0x388 0x38C 0x390 - 0x39C 0x3A0 N/A 0x380 0x384 0x388 0x38C 0x390 - 0x39C 0x3A0 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 72 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Register THDL Indirect Block Data THDL Reserved THDL Configuration THDL Reserved Reserved TCAS Indirect Channel and Time-slot Select TCAS Indirect Channel Data TCAS Framing Bit Threshold TCAS Reserved TCAS Idle Time-slot Fill Data TCAS Channel Disable TCAS Reserved TCAS SBI SPE1 Configuration Register #1 TCAS SBI SPE1 Configuration Register #2 TCAS SBI SPE2 Configuration Register #1 TCAS SBI SPE2 Configuration Register #2 TCAS SBI SPE3 Configuration Register #1 TCAS SBI SPE3 Configuration Register #2 TCAS Reserved FREEDM-32 FREEDM-32A672 FREEDM-84A672 PCI Offset Address Address 0x3A4 0x3A8 - 0x3AC 0x3B0 0x3B4 - 0x3BC 0x3C0 - 0x3FC 0x400 0x404 0x408 N/A 0x40C 0x410 0x414 - 0x47C N/A N/A N/A N/A N/A N/A N/A 0x3A4 0x3A8 - 0x3AC 0x3B0 0x3B4 - 0x3BC 0x3C0 - 0x3FC 0x400 0x404 0x408 N/A 0x40C 0x410 0x414 - 0x47C N/A N/A N/A N/A N/A N/A N/A 0x3A4 0x3A8 - 0x3AC 0x3B0 0x3B4 - 0x3BC 0x3C0 - 0x3FC 0x400 0x404 N/A 0x408 0x40C 0x410 0x414 - 0x43C 0x440 0x444 0x448 0x44C 0x450 0x454 0x458 - 0x47C PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 73 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Register TCAS Links #0 through #2 Configuration TCAS Links #3 through #31 Configuration TCAS Reserved PMON Status PMON Receive FIFO Overflow Count PMON Transmit FIFO Underflow Count PMON Configurable Count #1 PMON Configurable Count #2 PMON Reserved Reserved RAPI Control RAPI Reserved Reserved SBI EXTRACT Control SBI EXTRACT Reserved SBI EXTRACT Tributary RAM Indirect Access Address SBI EXTRACT Tributary RAM Indirect Access Control SBI EXTRACT Reserved SBI EXTRACT Tributary RAM Indirect Access Data FREEDM-32 FREEDM-32A672 FREEDM-84A672 PCI Offset Address Address 0x480 - 0x488 0x48C - 0x4FC N/A 0x500 0x504 0x508 0x50C 0x510 0x514 - 0x51C 0x520 - 0x7FC N/A N/A N/A N/A N/A N/A 0x480 - 0x488 0x48C - 0x4FC N/A 0x500 0x504 0x508 0x50C 0x510 0x514 - 0x51C 0x520 - 0x57C 0x580 0x584 - 0x5BC 0x5C0 - 0x5FC N/A N/A N/A 0x480 - 0x488 N/A 0x48C - 0x4FC 0x500 0x504 0x508 0x50C 0x510 0x514 - 0x51C 0x520 - 0x57C 0x580 0x584 - 0x5BC N/A 0x5C0 0x5C4 - 0x5C8 0x5CC N/A N/A 0x5D0 N/A N/A N/A N/A 0x5D4 0x5D8 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 74 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Register SBI EXTRACT Parity Error Interrupt Reason SBI EXTRACT Reserved TAPI Control TAPI Indirect Channel Provisioning TAPI Indirect Channel Data Register TAPI Reserved Reserved SBI INSERT Control SBI INSERT Reserved SBI INSERT Tributary RAM Indirect Access Address SBI INSERT Tributary RAM Indirect Access Control SBI INSERT Reserved SBI INSERT Tributary RAM Indirect Access Data SBI INSERT Reserved Reserved FREEDM-32 FREEDM-32A672 FREEDM-84A672 PCI Offset Address Address N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0x600 0x604 0x608 0x60C - 0x63C 0x640 - 0x7FC N/A N/A N/A N/A N/A N/A N/A N/A 0x5DC 0x5E0 - 0x5FC 0x600 0x604 0x608 0x60C - 0x63C 0x640 - 0x67C 0X680 0x684 - 0x688 0x68C 0x690 0x694 0x698 0x69C - 0x6FC 0x700 - 0x7FC Note: There are no PCI Configuration registers in the FREEDM-84A672 device. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 75 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE APPENDIX B - NEW NORMAL MODE REGISTERS The following registers are new for the FREEDM-84A672. The new registers are used to configure and control the SBI interface, the SBI Extracter and Inserter, the new RAPI672 and TAPI672 blocks, and line loopback for the increased number of links. Please refer to the Longform Datasheet[1] for detailed descriptions of these registers. FREEDM-84A672 Address 0x028 0x02C 0x038 0x03C 0x040 0x044 0x048 0x04C 0x140 0x144 0x148 0x14C 0x150 0x154 0x440 0x444 0x448 0x44C 0x450 0x454 0x580 Register FREEDM-84A672 Master SBI Interrupt Enable FREEDM-84A672 Master SBI Interrupt Status FREEDM-84A672 Master Line Loopback #3 FREEDM-84A672 Master Line Loopback #4 FREEDM-84A672 Master Line Loopback #5 FREEDM-84A672 Master Line Loopback #6 FREEDM-84A672 SBI DROP BUS Master Configuration FREEDM-84A672 SBI ADD BUS Master Configuration RCAS SBI SPE1 Configuration Register #1 RCAS SBI SPE1 Configuration Register #2 RCAS SBI SPE2 Configuration Register #1 RCAS SBI SPE2 Configuration Register #2 RCAS SBI SPE3 Configuration Register #1 RCAS SBI SPE3 Configuration Register #2 TCAS SBI SPE1 Configuration Register #1 TCAS SBI SPE1 Configuration Register #2 TCAS SBI SPE2 Configuration Register #1 TCAS SBI SPE2 Configuration Register #2 TCAS SBI SPE3 Configuration Register #1 TCAS SBI SPE3 Configuration Register #2 RAPI Control PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 76 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE FREEDM-84A672 Address 0x584 - 0x5BC 0x5C0 0x5C4 - 0x5C8 0x5CC 0x5D0 0x5D4 0x5D8 0x5DC 0x5E0 - 0x5FC 0x600 0x604 0x608 0x60C - 0x63C 0x680 0x684 - 0x688 0x68C 0x690 0x694 0x698 0x69C - 0x6FC RAPI Reserved SBI EXTRACT Control SBI EXTRACT Reserved Register SBI EXTRACT Tributary RAM Indirect Access Address SBI EXTRACT Tributary RAM Indirect Access Control SBI EXTRACT Reserved SBI EXTRACT Tributary RAM Indirect Access Data SBI EXTRACT Parity Error Interrupt Reason SBI EXTRACT Reserved TAPI Control TAPI Indirect Channel Provisioning TAPI Indirect Data Register TAPI Reserved SBI INSERT Control SBI INSERT Reserved SBI INSERT Tributary RAM Indirect Access Address SBI INSERT Tributary RAM Indirect Access Control SBI INSERT Reserved SBI INSERT Tributary RAM Indirect Access Data SBI INSERT Reserved PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 77 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE APPENDIX C - NON-APPLICABLE NORMAL MODE REGISTERS The following FREEDM-32 registers are no longer applicable in the FREEDM84A672. FREEDM-32 PCI Offset 0x010 0x020 0x040 0x044 - 0x07C 0x108 0x280 0x284 0x288 0x28C 0x290 0x294 0x298 0x29C 0x2A0 0x2A4 0x2A8 0x2AC Register FREEDM-32 Master Link Activity Monitor FREEDM-32 Master BERT Control GPIC Control GPIC Reserved RCAS Framing Bit Threshold RMAC Control RMAC Indirect Channel Provisioning RMAC Packet Descriptor Table Base LSW RMAC Packet Descriptor Table Base MSW RMAC Queue Base LSW RMAC Queue Base MSW RMAC Packet Descriptor Reference Large Buffer Free Queue Start RMAC Packet Descriptor Reference Large Buffer Free Queue Write RMAC Packet Descriptor Reference Large Buffer Free Queue Read RMAC Packet Descriptor Reference Large Buffer Free Queue End RMAC Packet Descriptor Reference Small Buffer Free Queue Start RMAC Packet Descriptor Reference Small Buffer Free Queue Write 0x18C - 0x1FC RCAS Link #3 through #31 Configuration PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 78 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE FREEDM-32 PCI Offset 0x2B0 0x2B4 0x2B8 0x2BC 0x2C0 0x2C4 0x2C8 - 0x2FC 0x300 0x304 0x308 0x30C 0x310 0x314 0x318 0x31C 0x320 0x324 0x328 0x32C 0x330 0x334 0x338 - 0x37C 0x408 Register RMAC Packet Descriptor Reference Small Buffer Free Queue Read RMAC Packet Descriptor Reference Small Buffer Free Queue End RMAC Packet Descriptor Reference Ready Queue Start RMAC Packet Descriptor Reference Ready Queue Write RMAC Packet Descriptor Reference Ready Queue Read RMAC Packet Descriptor Reference Ready Queue End RMAC Reserved TMAC Control TMAC Indirect Channel Provisioning TMAC Descriptor Table Base LSW TMAC Descriptor Table Base MSW TMAC Queue Base LSW TMAC Queue Base MSW TMAC Descriptor Reference Free Queue Start TMAC Descriptor Reference Free Queue Write TMAC Descriptor Reference Free Queue Read TMAC Descriptor Reference Free Queue End TMAC Descriptor Reference Ready Queue Start TMAC Descriptor Reference Ready Queue Write TMAC Descriptor Reference Ready Queue Read TMAC Descriptor Reference Ready Queue End TMAC Reserved TCAS Framing Bit Threshold 0x48C - 0x4FC TCAS Link #3 through #31 Configuration PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 79 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE APPENDIX D - MOVED NORMAL MODE REGISTERS The following registers have been moved when comparing its FREEDM-32 location to its FREEDM-84A672 location. Register FREEDM-x Master Line Loopback #1 FREEDM-x Master Line Loopback #2 RCAS Reserved FREEDM-32 PCI Offset 0x014 0x018 0x110 - 0x17C FREEDM-84A672 Address 0x030 0x034 0x108 0x110-0x13C 0x158 - 0x17C 0x18C - 0x1FC TCAS Reserved 0x414 - 0x47C 0x408 0x414 - 0x43C 0x458 - 0x47C 0x48C - 0x4FC PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 80 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE APPENDIX E - NORMAL MODE REGISTER BIT CHANGES The following normal mode registers have changed at the bit level from the FREEDM-32 to the FREEDM-84A672. Unless specified, register names, locations and comments refer to FREEDM-84A672 registers. Register 0x000 : FREEDM-84A672 Master Reset Bit FREEDM-84A672 Function 15 11 10 9 8 7 6 5 4 3 2 1 0 Reset TYPE[3] TYPE[2] TYPE[1] TYPE[0] ID[7] ID[6] ID[5] ID[4] ID[3] ID[2] ID[1] ID[0] Default 0 0 1 0 1 0 0 0 0 0 0 0 0 FREEDM-32 Function Reset Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Unused Default 0 X X X X X X X X X X X X Now also forces the APPI outputs tristate. New Device Type bits allow software to identify the device as the FREEDM-84A672 member of the FREEDM family of products. New Device ID bits allow software to identify the version level of FREEDM84A672. Comments PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 81 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Register 0x004 : FREEDM-84A672 Master Interrupt Enable Bit FREEDM-84A672 Function 14 13 12 11 10 9 8 7 6 1 0 TFOVRE TUNPVE TPRTYE Unused Unused Unused Unused Unused Unused Unused Unused Default 0 0 0 X X X X X X X X FREEDM-32 Function IOCE TDFQEE TDQRDYE TDQFE RPDRQEE RPDFQEE RPQRDYE RPQLFE RPQSFE PERRE SERRE Default 0 0 0 0 0 0 0 0 0 0 0 SERRE, PERRE, IOCE, and all queue-related interrupt enable bits are not used because queues and the PCI bus are not used for the FREEDM84A672. New interrupt enable bits are TPRTYE, TUNPVE, and TFOVRE. Comments Register 0x008 : FREEDM-84A672 Master Interrupt Status Bit FREEDM-84A672 Function 14 13 12 11 10 9 8 7 6 1 0 TFOVRI TUNPVI TPRTYI Unused Unused Unused Unused Unused Unused Unused Unused Default 0 0 0 X X X X X X X X FREEDM-32 Function IOCI TDFQEI TDQRDYI TDQFI RPDRQEI RPDFQEI RPQRDYI RPQLFI RPQSFI PERRI SERRI Default 0 0 0 0 0 0 0 0 0 0 0 SERRI, PERRI, IOCI, and all queue-related interrupt status bits are not used because queues and the PCI bus are not used for the FREEDM-84A672. New interrupt status bits are TPRTYI, TUNPVI, and TFOVRI. Comments PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 82 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Register 0x00C : FREEDM-84A672 Master Clock / Frame Pulse Activity Monitor and Accumulation Trigger Bit FREEDM-84A672 Function 13 12 3 2 1 TXCLKA RXCLKA C1FPA FASTCLKA REFCLKA Default X X X X X FREEDM-32 Function Unused Unused Unused Unused TBDA Default X X X X X Any-PHY transmit clock active bit. Any-PHY receive clock active bit. SBI frame pulse active bit. SBI fast clock active bit. SBI reference clock active bit. Transmit BERT data active bit is not applicable in the FREEDM-84A672. Comments Register 0x100 : RCAS Indirect Link and Time-slot Select Bit FREEDM-84A672 Function 12 11 10 9 8 7 6 LINK[6] LINK[5] LINK[4] LINK[3] LINK[2] LINK[1] LINK[0] Default 0 0 0 0 0 0 0 FREEDM-32 Function LINK[4] LINK[3] LINK[2] LINK[1] LINK[0] Unused Unused Default 0 0 0 0 0 X X Increase in the number of receive links from 32 to 84. Comments PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 83 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Register 0x104 : RCAS Indirect Channel Data Bit FREEDM-84A672 Function 15 14 9 8 7 CDLBEN PROV CHAN[9] CHAN[8] CHAN[7] Default 0 0 0 0 0 FREEDM-32 Function Unused Unused CDLBEN PROV Unused Default X X 0 0 X Increase in size of CHAN from 7 bits to 10 bits as the result of increase in HDLC channels from 128 to 672. Comments Register 0x10C : RCAS Channel Disable Bit FREEDM-84A672 Function 9 8 7 DCHAN[9] DCHAN[8] DCHAN[7] Default 0 0 0 FREEDM-32 Function Unused Unused Unused Default X X X Increase in size of DCHAN from 7 bits to 10 bits as the result of increase in HDLC channels from 128 to 672. Comments Registers 0x180 - 0x188 : RCAS Links #0 to #2 Configuration Bit FREEDM-84A672 Function 4 2 1 0 Reserved Reserved Reserved Reserved Default 0 0 0 0 FREEDM-32 Function Unused BSYNC E1 CEN Default X 0 0 0 The reserved bits must be set low for correct operation of the FREEDM-84A672. CEN, E1 and BSYNC are not applicable in the FREEDM-84A672. Comments PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 84 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Register 0x200 : RHDL Indirect Channel Select Bit FREEDM-84A672 Function 9 8 7 CHAN[9] CHAN[8] CHAN[7] Default 0 0 0 FREEDM-32 Function Unused Unused Unused Default X X X Increase in size of CHAN from 7 bits to 10 bits as the result of increase in HDLC channels from 128 to 672. Comments Register 0x204 : RHDL Indirect Channel Data #1 Bit FREEDM-84A672 Function 14 STRIP Default 0 FREEDM-32 Function CRC[1] Default 0 CRC[1] moved to bit 11 of Register 0x208 of the FREEDM-84A672. CRC[0] moved to bit 10 of Register 0x208 of the FREEDM-84A672. Comments 13 DELIN 0 CRC[0] 0 12 11 TAVAIL Reserved X X STRIP DELIN 0 0 Reserved bit must be set low for correct operation of the FREEDM-84A672. Increase in size of FPTR from 9 bits to 11 bits as the result of increase in addressable descriptors from 512 to 2048. 10 9 FPTR[10] FPTR[9] X X TAVAIL Unused X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 85 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Register 0x208 : RHDL Indirect Channel Data #2 Bit FREEDM-84A672 Function 11 CRC[1] Default 0 FREEDM-32 Function Unused Default X CRC[1] moved from bit 14 of Register 0x204 of the FREEDM-32. CRC[0] moved from bit 13 of Register 0x204 of the FREEDM-32. XFER increased from 3 bits to 4 bits to support larger data transfers. Comments 10 CRC[0] 0 Unused X 3 XFER[3] 0 Unused X Register 0x210 : RHDL Indirect Block Select Bit FREEDM-84A672 Function 11 Reserved Default X FREEDM-32 Function Unused Default X Reserved bit must be set low for correct operation of FREEDM-84A672. BLOCK increased from 9 bits to 11 bits as the result of increase in addressable blocks from 512 to 2048. Comments 10 9 BLOCK[10] BLOCK[9] X X Unused Unused X X Register 0x214 : RHDL Indirect Block Data Bit FREEDM-84A672 Function 11 Reserved Default X FREEDM-32 Function Unused Default X Reserved bit must be set low for correct operation of FREEDM-84A672. BPTR increased from 9 bits to 11 bits as the result of increase in addressable blocks from 512 to 2048. Comments 10 9 BPTR[10] BPTR[9] X X Unused Unused X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 86 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Register 0x220 : RHDL Configuration Bit FREEDM-84A672 Function 2 1 0 Unused Unused Unused Default X X X FREEDM-32 Function Reserved[2] Reserved[1] Reserved[0] Default 1 1 1 These reserved bits are no longer used in the FREEDM-84A672. Comments Register 0x380 : THDL Indirect Channel Select Bit FREEDM-84A672 Function 9 8 7 CHAN[9] CHAN[8] CHAN[7] Default 0 0 0 FREEDM-32 Function Unused Unused Unused Default X X X Increase in size of CHAN from 7 bits to 10 bits as the result of increase in HDLC channels from 128 to 672. Comments Register 0x384 : THDL Indirect Channel Data #1 Bit FREEDM-84A672 Function 12 DELIN Default X FREEDM-32 Function IDLE Default 0 IDLE moved to bit 14 of Register 0x38C of the FREEDM-84A672. Reserved bit must be set low for correct operation of FREEDM-84A672. Increase in size of FPTR from 9 bits to 11 bits as the result of increase in addressable descriptors from 512 to 2048. Comments 11 Reserved X DELIN 0 10 9 FPTR[10] FPTR[9] 0 0 Unused Unused X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 87 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Register 0x388 : THDL Indirect Channel Data #2 Bit FREEDM-84A672 Function 14 11 Reserved Reserved Default 0 0 FREEDM-32 Function PRIORITYB Unused Default 0 X Reserved bit must be set low for correct operation of the FREEDM-84A672. PRIORITYB is not used in the FREEDM-84A672. 10 9 FLEN[10] FLEN[9] 0 0 Unused Unused X X Increase in size of FLEN from 9 bits to 11 bits as the result of increase in addressable descriptors from 512 to 2048. Comments Register 0x38C : THDL Indirect Channel Data #3 Bit FREEDM-84A672 Function 14 IDLE Default 0 FREEDM-32 Function Unused Default X IDLE moved from bit 12 of Register 0x384 of the FREEDM-32. XFER increased from 3 bits to 4 bits to support larger data transfers. Comments 3 XFER[3] 0 Unused X Register 0x3A0 : THDL Indirect Block Select Bit FREEDM-84A672 Function 11 Reserved Default X FREEDM-32 Function Unused Default X Reserved bit must be set low for correct operation of FREEDM-84A672. BLOCK increased from 9 bits to 11 bits as the result of increase in addressable blocks from 512 to 2048. Comments 10 9 BLOCK[10] BLOCK[9] 0 0 Unused Unused X X PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 88 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Register 0x3A4 : THDL Indirect Block Data Bit FREEDM-84A672 Function 11 Reserved Default X FREEDM-32 Function Unused Default X Reserved bit must be set low for correct operation of FREEDM-84A672. BPTR increased from 9 bits to 11 bits as the result of increase in addressable blocks from 512 to 2048. Comments 10 9 BPTR[10] BPTR[9] 0 0 Unused Unused X X Register 0x3B0 : THDL Configuration Bit FREEDM-84A672 Function 7 3 2 1 0 Reserved Reserved Reserved Reserved Reserved Default 0 0 0 0 0 FREEDM-32 Function BURSTEN Unused BURST[2] BURST[1] BURST[0] Default 0 X 0 0 0 Reserved bits must be set low for correct operation of FREEDM-84A672. The DMA burst length feature is not used in the FREEDM-84A672. Comments Register 0x400 : TCAS Indirect Link and Time-slot Select Bit FREEDM-84A672 Function 12 11 10 9 8 7 6 LINK[6] LINK[5] LINK[4] LINK[3] LINK[2] LINK[1] LINK[0] Default 0 0 0 0 0 0 0 FREEDM-32 Function LINK[4] LINK[3] LINK[2] LINK[1] LINK[0] Unused Unused Default 0 0 0 0 0 X X Increase in the number of transmit links from 32 to 84. Comments PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 89 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE Register 0x404 : TCAS Indirect Channel Data Bit FREEDM-84A672 Function 15 9 8 7 PROV CHAN[9] CHAN[8] CHAN[7] Default 0 0 0 0 FREEDM-32 Function Unused Unused PROV Unused Default X X 0 X Increase in size of CHAN from 7 bits to 10 bits as the result of increase in HDLC channels from 128 to 672. Comments Register 0x410 : TCAS Channel Disable Bit FREEDM-84A672 Function 9 8 7 DCHAN[9] DCHAN[8] DCHAN[7] Default 0 0 0 FREEDM-32 Function Unused Unused Unused Default X X X Increase in size of DCHAN from 7 bits to 10 bits as the result of increase in HDLC channels from 128 to 672. Comments Registers 0x480 - 0x488 : TCAS Links #0 to #2 Configuration Bit FREEDM-84A672 Function 4 2 1 0 Reserved Reserved Reserved Reserved Default 0 0 0 0 FREEDM-32 Function Unused BSYNC E1 CEN Default X 0 0 0 The reserved bits must be set low for correct operation of the FREEDM-84A672. CEN, E1 and BSYNC are not applicable in the FREEDM-84A672. Comments PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE 90 ADVANCE APPLICATION NOTE PMC-990716 ISSUE 1 PM7385 FREEDM-84A672 PROGRAMMER'S GUIDE CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com Document Information: Corporate Information: Application Information: Web Site: None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1999 PMC-Sierra, Inc. PMC-990716 (A1) date: June 1999 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE |
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